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Arnel M. Fajardo, Beaverton US

Arnel M. Fajardo, Beaverton, OR US

Patent application numberDescriptionPublished
20080202922HYBRID ELECTRO-DEPOSITION OF SOFT MAGNETIC COBALT ALLOY FILMS - A hybrid electro-deposition process for soft magnetic cobalt alloy films comprises providing a plating bath that includes cobalt and a reducing agent, providing a cobalt-containing anode in the plating bath coupled to a power supply, providing a substrate in the plating bath coupled to the power supply, wherein the substrate functions as a cathode, applying a magnetic field across the plating bath, and applying an electrical current to the plating bath by way of the power supply to cause the cobalt to deposit onto the substrate and form a soft magnetic film.08-28-2008
20080237051Method and plating bath for depositing a magnetic film - A cobalt-iron-boron (CoFeB) film (10-02-2008
20080238593Apparatus, method, and system capable of producing a moveable magnetic field - An apparatus capable of producing a moveable magnetic field includes a moveable support structure (10-02-2008
20080241575SELECTIVE ALUMINUM DOPING OF COPPER INTERCONNECTS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include heating a substrate comprising a patterned metallic region to about 145 C or below in a reaction space, introducing an aluminum co-reactant into the reaction space, wherein an aluminum material is formed on the patterned metallic region, but not on non-metallic regions.10-02-2008
20100098960MAGNETIC INSULATOR NANOLAMINATE DEVICE FOR INTEGRATED SILICON VOLTAGE REGULATORS - A magnetic insulator nanolaminate device comprises a metal magnetic layer formed on a substrate, an insulating layer formed on the metal magnetic layer, wherein the insulating layer is formed by nitriding a portion of the metal magnetic layer, a chelating group layer formed on the insulating layer, and a metal seed layer bonded to the chelating group layer. The magnetic insulator nanolaminate device may be formed by depositing a metal layer on a substrate, converting a portion of the metal layer into an insulating layer using a nitridation process, and depositing a metal seed layer onto the insulating layer using a metal immobilization process, wherein the metal seed layer enables the deposition of a metal layer onto the insulating layer.04-22-2010
20100140804Dual metal interconnects for improved gap-fill, reliability, and reduced capacitance - Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed.06-10-2010
20100276763LGA SUBSTRATE AND METHOD OF MAKING SAME - A transistor comprises a gate (11-04-2010
20100283570NANO-ENCAPSULATED MAGNETIC PARTICLE COMPOSITE LAYERS FOR INTEGRATED SILICON VOLTAGE REGULATORS - A method of forming an integrated silicon voltage regulator (ISVR) comprises providing a nano-encapsulated magnetic particle (NEMP) suspension, depositing a first layer of the NEMP suspension on an integrated circuit (IC) device, curing the first layer of the NEMP suspension to form a first NEMP composite layer, forming at least one inductor wire on the NEMP composite layer, depositing an interlayer dielectric material over the inductor wire, depositing a second layer of the NEMP suspension on the interlayer dielectric material, and curing the second layer of the NEMP suspension to form a second NEMP composite layer.11-11-2010
20110079910DUAL METAL INTERCONNECTS FOR IMPROVED GAP-FILL, RELIABILITY, AND REDUCED CAPACITANCE - Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed.04-07-2011

Patent applications by Arnel M. Fajardo, Beaverton, OR US