| Patent application number | Description | Published |
|---|
| 20080254204 | DIELECTRIC APPARATUS AND ASSOCIATED METHODS - In an embodiment of the invention, an amorphous phase dielectric material is selectively formed over a substrate. The amorphous phase dielectric material is then converted into a crystalline phase dielectric material. | 10-16-2008 |
| 20080290448 | Semiconductor devices and methods of manufacture thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion. | 11-27-2008 |
| 20090001502 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer. | 01-01-2009 |
| 20090174027 | INTEGRATED CIRCUIT INCLUDING ISOLATION REGIONS SUBSTANTIALLY THROUGH SUBSTRATE - An integrated circuit including a substrate and trench isolation regions. The substrate supports a device. The trench isolation regions are configured to laterally isolate the device. The trench isolation regions extend substantially through the substrate. | 07-09-2009 |
| 20100008122 | Memory Device And Method For Making Same - An embodiment relates to a memory cell comprising a programmable resistance memory element electrically coupled to a heterojunction bipolar transistor. | 01-14-2010 |
| 20100197112 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion. | 08-05-2010 |
| 20100207238 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer. | 08-19-2010 |
| Patent application number | Description | Published |
|---|
| 20090135655 | Embedded Flash Memory Devices on SOI Substrates and Methods of Manufacture Thereof - Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices. | 05-28-2009 |
| 20090146146 | Semiconductor Device formed in a Recrystallized Layer - A semiconductor device includes a substrate that includes a first layer and a recrystallized layer on the first layer. The first layer has a first intrinsic stress and the recrystallized layer has a second intrinsic stress. A transistor is formed in the recrystallized layer. The transistor includes a source region, a drain region, and a charge carrier channel between the source and drain regions. The second intrinsic stress is aligned substantially parallel to the charge carrier channel. | 06-11-2009 |
| 20100149882 | Methods of Operating Embedded Flash Memory Devices - Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices. | 06-17-2010 |
| 20100203703 | Deep Trench Isolation Structures and Methods of Formation Thereof - Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material. | 08-12-2010 |
