| Patent application number | Description | Published |
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| 20090326664 | POSTERIOR CRUCTIATE-RETAINING ORTHOPAEDIC KNEE PROSTHESIS HAVING CONTROLLED CONDYLAR CURVATURE - An orthopaedic knee prosthesis includes a tibial bearing and a femoral component configured to articulate with the tibial bearing. The femoral component includes a condyle surface curved in the sagittal plane. The radius of curvature of the condyle surface decreases gradually between early-flexion and mid-flexion. Additionally, in some embodiments, the radius of curvature may be increased during mid-flexion. | 12-31-2009 |
| 20090326665 | POSTERIOR STABILIZED ORTHOPAEDIC KNEE PROSTHESIS HAVING CONTROLLED CONDYLAR CURVATURE - An orthopaedic knee prosthesis includes a tibial bearing and a femoral component configured to articulate with the tibial bearing. The femoral component includes a posterior cam configured to contact a spine of the tibial bearing and a condyle surface curved in the sagittal plane. The radius of curvature of the condyle surface decreases gradually between early-flexion and mid-flexion. Additionally, in some embodiments, the radius of curvature of the condyle surface may be increased during mid-flexion. | 12-31-2009 |
| 20090326667 | ORTHOPAEDIC FEMORAL COMPONENT HAVING CONTROLLED CONDYLAR CURVATURE - An orthopaedic knee prosthesis includes a femoral component having a condyle surface. The condyle surface is defined by one or more radii of curvatures, which are controlled to reduce or delay the onset of anterior translation of the femoral component relative to a tibial bearing. | 12-31-2009 |
| 20100036500 | ORTHOPAEDIC KNEE PROSTHESIS HAVING CONTROLLED CONDYLAR CURVATURE - An orthopaedic knee prosthesis includes a femoral component having a condyle surface. The condyle surface is defined by one or more radii of curvatures, which are controlled to reduce or delay the onset of anterior translation of the femoral component relative to a tibial bearing. | 02-11-2010 |
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| 20090140418 | METHOD FOR INTEGRATING POROUS LOW-K DIELECTRIC LAYERS - Described herein are methods for integrating low-k dielectric layers with various interconnect structures. In one embodiment, a method for restoring a porous dielectric layer includes forming an opening in the porous low-k dielectric layer. The method further includes forming an opening in a barrier layer. The method further includes depositing a restoring dielectric layer to seal a surface layer of pores of the porous dielectric layer. In one embodiment, the restoring dielectric layer is non-porous and hydrophobic to prevent the porous dielectric layer from adsorbing moisture and consequently increasing the dielectric constant of the porous dielectric layer. The method further includes performing a clean operation on the interconnect structure prior to metallization. The method further includes depositing, masking, and etching a metal layer. | 06-04-2009 |
| 20090286402 | METHOD FOR CRITICAL DIMENSION SHRINK USING CONFORMAL PECVD FILMS - A method and apparatus for forming narrow vias in a substrate is provided. A pattern recess is etched into a substrate by conventional lithography. A thin conformal layer is formed over the surface of the substrate, including the sidewalls and bottom of the pattern recess. The thickness of the conformal layer reduces the effective width of the pattern recess. The conformal layer is removed from the bottom of the pattern recess by anisotropic etching to expose the substrate beneath. The substrate is then etched using the conformal layer covering the sidewalls of the pattern recess as a mask. The conformal layer is then removed using a wet etchant. | 11-19-2009 |
| 20100022091 | METHOD FOR PLASMA ETCHING POROUS LOW-K DIELECTRIC LAYERS - Described herein are methods and apparatuses for etching low-k dielectric layers to form various interconnect structures. In one embodiment, the method includes forming an opening in a resist layer. The method further includes etching a porous low-k dielectric layer with a process gas mixture that includes a fluorocarbon gas and a carbon dioxide (CO | 01-28-2010 |
| 20100043821 | METHOD OF PHOTORESIST REMOVAL IN THE PRESENCE OF A LOW-K DIELECTRIC LAYER - Described herein are methods and apparatus for removing photoresist in the presence of low-k dielectric layers. In one embodiment, the method includes exciting a first mixture of gases having a ratio of a flow rate of reducing process gas to a flow rate of an oxygen-containing process gas that is between 1:1 and 100:1 to generate a first reactive gas mixture. Next, the method includes exposing the photoresist layer that overlays the low-k dielectric layer on a substrate to the first reactive gas mixture to selectively remove the photoresist layer from the dielectric layer. Next, the method includes exposing the photoresist layer to a second reactive gas mixture to selectively remove the photoresist layer from the dielectric layer. The first and second reactive gas mixtures contain substantially no ions when the substrate is exposed to these mixtures in order to minimize damage to the low-k dielectric layer. | 02-25-2010 |
| 20100078825 | METHOD FOR FABRICATING INTERCONNECT STRUCTURES FOR SEMICONDUCTOR DEVICES - Described herein are methods for fabricating dual-damascene interconnect structures. In one embodiment, the interconnect structures are fabricated with a dual-damascene method having trenches then vias formed. The method includes novel liner depositions after the trench and via etches. The method includes etching trenches in a dielectric layer. Next, the method includes depositing a first liner layer on the dielectric layer. Next, the method includes etching vias in the dielectric layer and an etch stop layer. Next, the method includes depositing a second liner layer on the first liner layer. The second liner layer is deposited on the exposed surfaces of the first liner layer, dielectric layer, etch stop layer, and the first metal layer. Then, a second metal layer is deposited on the second liner layer. | 04-01-2010 |
| 20110151590 | APPARATUS AND METHOD FOR LOW-K DIELECTRIC REPAIR - A method, a system and a computer readable medium for integrated in-vacuo repair of low-k dielectric thin films damaged by etch and/or strip processing. A repair chamber is integrated onto a same platform as a plasma etch and/or strip chamber to repair a low-k dielectric thin film without breaking vacuum between the damage event and the repair event. UV radiation may be provided on the integrated etch/repair platform in any combination of before, after, or during the low-k repair treatment to increase efficacy of the repair treatment and/or stability of repair. | 06-23-2011 |
| 20110253670 | METHODS FOR ETCHING SILICON-BASED ANTIREFLECTIVE LAYERS - Methods for etching silicon-based antireflective layers are provided herein. In some embodiments, a method of etching a silicon-based antireflective layer may include providing to a process chamber a substrate having a multiple-layer resist thereon, the multiple-layer resist comprising a patterned photoresist layer defining features to be etched into the substrate disposed above a silicon-based antireflective coating; and etching the silicon-based antireflective layer through the patterned photoresist layer using a plasma formed from a process gas having a primary reactive agent comprising a chlorine-containing gas. In some embodiments, the chlorine-containing gas is chlorine (Cl | 10-20-2011 |
