| Patent application number | Description | Published |
|---|
| 20090027964 | SEMICONDUCTOR MEMORY DEVICE HAVING PLURAL WORD LINES ARRANGED AT NARROW PITCH AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a memory cell array which includes at least one memory unit having a preset number of memory cell transistors and a selection gate transistor on a source side, a preset number of word lines respectively connected to control gates of the preset number of memory cell transistors, and a selection gate line on a source side connected to a gate electrode of the selection gate transistor on the source side. In the semiconductor memory device, a distance C between the selection gate line at least on the source side and one of the word lines adjacent thereto is set to n*A+(n−1)B, where n is an integer greater than or equal to 2, A indicates the pitch between adjacent ones of the preset number of word lines, and B indicates the width of each of the preset number of word lines. | 01-29-2009 |
| 20090039408 | NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory of an aspect of the present invention comprises a first element isolation insulating film containing an organic substance which surrounds a first region, a memory cell arranged in the first region, a second element isolation insulating film containing an organic substance which surrounds a second region, a peripheral transistor arranged in the second region, and a first impurity layer which is provided in the semiconductor substrate along a side surface of the second element isolation insulating film. | 02-12-2009 |
| 20090194841 | SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the second high-voltage insulated-gate field effect transistor from each other; a second device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the third high-voltage insulated-gate field effect transistor from each other; a first impurity diffusion layer of the first conductivity type that is formed below the first device isolation insulating film; and a second impurity diffusion layer of the first conductivity type that is formed below the second device isolation insulating film. | 08-06-2009 |
| 20090256190 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element isolation film embedded into the element isolation groove; gate insulating films each formed on corresponding one of the active areas and having a first end portion that overhangs from the corresponding active area onto the element isolation area at one side and a second end portion that overhangs from the corresponding active area onto the element isolation area at the other side, wherein an overhang of the first end portion has a different length from a length of an overhang of the second end portion. | 10-15-2009 |
