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Arai, Kyoto
Katsujirou Arai, Kyoto JP
| Patent application number | Description | Published |
|---|---|---|
| 20090053866 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, METHOD FOR DRIVING THE SAME, AND METHOD FOR FABRICATING THE SAME - A p-type source region | 02-26-2009 |
Katsuya Arai, Kyoto JP
| Patent application number | Description | Published |
|---|---|---|
| 20080210978 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts. | 09-04-2008 |
| 20090059453 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes an external pad, a ground line, a first protection circuit between the external pad and the ground line, and a second protection circuit between the external pad and the ground line. The second protection circuit is formed by a first protection element, a second protection element, and a resistor. With this structure, the resistance value of the resistor is set to an arbitrary value, so that an unnecessary current which would be generated at the time of power-off of the LSI can be decreased to a value which does not deteriorate the reliability of the LSI. | 03-05-2009 |
| 20100148267 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a well | 06-17-2010 |
| 20100207163 | SEMICONDUCTOR DEVICE INCLUDING ELECTROSTATIC-DISCHARGE PROTECTION CIRCUIT - A semiconductor device includes a protected circuit and an electrostatic-discharge protection circuit. The electrostatic-discharge protection circuit includes a first well of a first conductivity type and a second well of a second conductivity type formed in contact with each other in a semiconductor substrate, a first impurity diffusion layer of the first conductivity type and a third impurity diffusion layer of the second conductivity type formed apart from each other in the first well, and a second impurity diffusion layer of the second conductivity type and a fourth impurity diffusion layer of the first conductivity type formed apart from each other in the second well. The second and the third impurity diffusion layers are formed adjacent to each other interposing an element isolation region provided across a border between the first and the second wells. | 08-19-2010 |
| 20110102954 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first functional circuit block; a second functional circuit block; a relay circuit block; a first protection circuit block; and a second protection circuit block. The first protection circuit block includes an ESD protection circuit connected between either one of a first high-voltage power supply line and a first low-voltage power supply line, and either one of a third high-voltage power supply line and a third low-voltage power supply line. The second protection circuit block includes an ESD protection circuit connected between either one of a second high-voltage power supply line and a second low-voltage power supply line, and either one of the third high-voltage power supply line and the third low-voltage power supply line. | 05-05-2011 |
Kazuo Arai, Kyoto JP
| Patent application number | Description | Published |
|---|---|---|
| 20110164341 | STATIC ELIMINATING SHEET, STATIC ELIMINATING SYSTEM FOR SHEETS, AND SIMULTANEOUS DESIGN MOLDING METHOD, PRINTING METHOD, AND DEPOSITION METHOD USING STATIC ELIMINATING SHEET - There are provided a substrate sheet, a plurality of design portions arranged independently from each other along a longitudinal direction of the substrate sheet and each including at least a conductive material portion, and a band-shaped static eliminating band portion extending continuously along the longitudinal direction of the substrate sheet and electrically connecting the conductive material portions in the plurality of design portions to each other. | 07-07-2011 |
Mitsuru Arai, Kyoto JP
| Patent application number | Description | Published |
|---|---|---|
| 20110102085 | DIFFERENTIAL AMPLIFIER - A high-gain differential amplifier that is capable of high speed operation is provided. A differential amplifier that outputs a signal representing a difference between signals respectively inputted to first and second input terminals and a phase-inverted signal thereof via first and second output terminals respectively, is provided with a first switching element that makes a short-circuit between the first input terminal and the second output terminal when turned on, a second switching element that makes a short-circuit between the second input terminal and the first output terminal when turned on, and a third switching element that makes a short-circuit between the first output terminal and the second output terminal when turned on. The third switching element is set to an ON state for a predetermined period while the first and second switching elements are set to an OFF state. Subsequently, the third switching element is switched to the OFF state and both of the first and second switching elements are switched to the ON state. | 05-05-2011 |
Yoshiyuki Arai, Kyoto JP
| Patent application number | Description | Published |
|---|---|---|
| 20100014262 | MODULE WITH EMBEDDED ELECTRONIC COMPONENTS - In a module with embedded electronic components, connection electrodes are formed on the component mounting surface of a substrate. The electrode portions of each of the electronic components are placed on the individual connection electrodes and connected in fixed relation thereto by using a solder. The electronic components are encapsulated in an encapsulating resin. When the distance between the lower surface of the main body portion of each of the electronic components and the component mounting surface is assumed to be a and the thickness of the portion of the encapsulating resin which is located above the main body portion of the electronic component is assumed to be b, if b/a is set to a value of not more than 6, it becomes possible to prevent, when the module with embedded electronic components is reflow-mounted on a printed wiring substrate or the like, the occurrence of a short circuit failure resulting from the melting and flowing of the solder which causes a short circuit between the two electrode portions. | 01-21-2010 |