| Patent application number | Description | Published |
|---|
| 20080224164 | Light Emitting Device with a Nanocrystalline Silicon Embedded Insulator Film - A light emitting device using a silicon (Si) nanocrystalline Si insulating film is presented with an associated fabrication method. The method provides a doped semiconductor or metal bottom electrode. Using a high density plasma-enhanced chemical vapor deposition (HDPECVD) process, a Si insulator film is deposited overlying the semiconductor electrode, having a thickness in a range of 30 to 200 nanometers (nm). For example, the film may be SiOx, where X is less than 2, Si3Nx, where X is less than 4, or SiCx, where X is less than 1. The Si insulating film is annealed, and as a result, Si nanocrystals are formed in the film. Then, a transparent metal electrode is formed overlying the Si insulator film. An annealed Si nanocrystalline SiOx film has a turn-on voltage of less than 20 volts, as defined with respect to a surface emission power of greater than 0.03 watt per square meter. | 09-18-2008 |
| 20080246088 | Self-Aligned Lightly Doped Drain Recessed-Gate Thin-Film Transistor - A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench. | 10-09-2008 |
| 20080266689 | Non-stoichiometric SiOxNy optical filters - A non-stoichiometric SiO | 10-30-2008 |
| 20080272816 | Inverter with Four-Transistor Schmitt Trigger - A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region. | 11-06-2008 |
| 20080305566 | Silicon Nanocrystal Embedded Silicon Oxide Electroluminescence Device with a Mid-Bandgap Transition Layer - A method is provided for forming a silicon (Si) nanocrystal embedded Si oxide electroluminescence (EL) device with a mid-bandgap transition layer. The method provides a highly doped Si bottom electrode, and forms a mid-bandgap electrically insulating dielectric film overlying the electrode. A Si nanocrystal embedded SiOx film layer is formed overlying the mid-bandgap electrically insulating dielectric film, where X is less than 2, and a transparent top electrode overlies the Si nanocrystal embedded SiOx film layer. The bandgap of the mid-bandgap dielectric film is about half that of the bandgap of the Si nanocrystal embedded SiOx film. In one aspect, the Si nanocrystal embedded SiOx film has a bandgap (Eg) of about 10 electronvolts (eV) and mid-bandgap electrically insulating dielectric film has a bandgap of about 5 eV. By dividing the high-energy tunneling processes into two lower energy tunneling steps, potential damage due to high power hot electrons is reduced. | 12-11-2008 |
| 20090033206 | Graded Junction Silicon Nanocrystal Embedded Silicon Oxide Electroluminescence Device - A silicon (Si) nanocrystal embedded Si oxide electroluminescence (EL) device and associated fabrication process are presented. The method provides a substrate bottom electrode, and forms a plurality of Si nanocrystal embedded SiOx film layers overlying the bottom electrode, where X is less than 2. Each SiOx film layer has a Si excess concentration in a range of about 5 to 30%. The outside film layers sandwich an inner film layer having a lower concentration of Si nanocrystals. Alternately stated, the outside Si nanocrystal embedded SiOx film layers have a higher electrical conductivity than a sandwiched inner film layer. A transparent top electrode is formed over the plurality of Si nanocrystal embedded SiOx film layers. The plurality of Si nanocrystal embedded SiOx film layers are deposited using a high density plasma-enhanced chemical vapor deposition (HD PECVD) process. The HD PECVD process initially deposits SiOx film layers, which are subsequently annealed. | 02-05-2009 |
| 20090033207 | High Quantum Efficiency Silicon Nanoparticle Embedded SiOxNy Luminescence Device - A method is provided for fabricating a high quantum efficiency silicon (Si) nanoparticle embedded SiO | 02-05-2009 |
| 20090040599 | Optical Waveguide Amplifier Using High Quantum Efficiency Silicon Nanocrystal Embedded Silicon Oxide - A method is provided for optical amplification using a silicon (Si) nanocrystal embedded silicon oxide (SiOx) waveguide. The method provides a Si nanocrystal embedded SiOx waveguide, where x is less than 2, having a quantum efficiency of greater than 10%. An optical input signal is supplied to the Si nanocrystal embedded SiOx waveguide, having a first power at a first wavelength in the range of 700 to 950 nm. The Si nanocrystal embedded SiOx waveguide is pumped with an optical source having a second power at a second wavelength in a range of 250 to 550 nm. As a result, an optical output signal having a third power is generated, greater than the first power, at the first wavelength. In one aspect, the third power increases in response to the length of the waveguide strip. | 02-12-2009 |
| 20090058266 | Fabrication of a Semiconductor Nanoparticle Embedded Insulating Film Luminescence Device - A method is provided for fabricating a semiconductor nanoparticle embedded Si insulating film for short wavelength luminescence applications. The method provides a bottom electrode, and deposits a semiconductor nanoparticle embedded Si insulating film, including the element of N, O, or C, overlying the bottom electrode. After annealing, a semiconductor nanoparticle embedded Si insulating film has a peak photoluminescence (PL) at a wavelength in the range of 475 to 750 nanometers. | 03-05-2009 |
| 20090078940 | Location-controlled crystal seeding - A structure with location-controlled crystallization of an active semiconductor film using a crystal seed has been provided, along with an associated fabrication method. The method forms a first semiconductor film overlying a substrate having a crystallographic orientation. Typically, the structure is polycrystalline or single-crystal. The first semiconductor film is selectively etched, forming a seed region. An insulator is formed with an opening, exposing the seed region. An amorphous second semiconductor film is formed over the insulator layer. The second semiconductor film is laser annealed, partially melting the seed region. Crystal grains are laterally grown in the second semiconductor film having the same crystallographic orientation as the seed region. In TFT fabrication an etching is typically performed to remove the second semiconductor film overlying the seed region, and a transistor active region is formed in the remaining second semiconductor film. | 03-26-2009 |
| 20090115311 | Fabrication of a Semiconductor Nanoparticle Embedded Insulating Film Electroluminescence Device - A method is provided for fabricating a semiconductor nanoparticle embedded Si insulating film for electroluminescence (EL) applications. The method provides a bottom electrode, and deposits a semiconductor nanoparticle embedded Si insulating film, including an element selected from a group consisting of N and C, overlying the bottom electrode. After annealing, a semiconductor nanoparticle embedded Si insulating film is formed having an extinction coefficient (k) in a range of 0.01-1.0, as measured at about 632 nanometers (nm), and a current density (J) of greater than 1 Ampere per square centimeter (A/cm | 05-07-2009 |
| 20090217968 | Silicon Oxide-Nitride-Carbide with Embedded Nanocrystalline Semiconductor Particles - A solar call is provided along with a method for forming a semiconductor nanocrystalline silicon insulating thin-film with a tunable bandgap. The method provides a substrate and introduces a silicon (Si) source gas with at least one of the following source gases: germanium (Ge), oxygen, nitrogen, or carbon into a high density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. A SiOxNyCz thin-film embedded with a nanocrystalline semiconductor material is deposited overlying the substrate, where x, y, z≧0, and the semiconductor material is Si, Ge, or a combination of Si and Ge. As a result, a bandgap is formed in the SiOxNyCz thin-film, in the range of about 1.9 to 3.0 electron volts (eV). Typically, the semiconductor nanoparticles have a size in a range of 1 to 20 nm. | 09-03-2009 |
| 20090232449 | Erbium-Doped Silicon Nanocrystalline Embedded Silicon Oxide Waveguide - An erbium (Er)-doped silicon (Si) nanocrystalline embedded silicon oxide (SiOx) waveguide and associated fabrication method are presented. The method provides a bottom layer, and forms an Er-doped Si nanocrystalline embedded SiOx film waveguide overlying the bottom layer, having a minimum optical attenuation at about 1540 nanometers (nm). Then, a top layer is formed overlying the Er-doped SiOx film. The Er-doped SiOx film is formed by depositing a silicon rich silicon oxide (SRSO) film using a high density plasma chemical vapor deposition (HDPCVD) process and annealing the SRSO film. After implanting Er | 09-17-2009 |
| 20090250700 | Crystalline Semiconductor Stripe Transistor - A transistor with crystalline semiconductor stripes and an associated fabrication process are provided. The method provides a substrate, and deposits a semiconductor layer overlying the substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated semiconductor material, a transistor active semiconductor region is formed including a plurality of crystalline semiconductor stripes oriented along parallel axes. In one aspect, a channel region is formed from the plurality of oriented crystalline semiconductor stripes, and the method forms a gate dielectric overlying the channel region, with a gate electrode overlying the gate dielectric. In another aspect, forming the transistor active semiconductor region includes forming source, drain, and channel regions from the plurality of oriented crystalline semiconductor stripes. | 10-08-2009 |
| 20090250791 | Crystalline Semiconductor Stripes - Crystalline semiconductor stripes and an associated fabrication process are provided. The method provides an insulator substrate, and deposits a semiconductor layer overlying the insulator substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated semiconductor material, oriented crystalline semiconductor stripes are formed on the insulator substrate. The crystalline semiconductor stripes are aligned approximately with a straight line stripe axis overlying a top surface of the insulating substrate. Each crystalline semiconductor stripe includes a plurality of consecutive ring segments aligned with the stripe axis. The rings segments have a width about equal to the laser annealing process step distance. The crystalline semiconductor stripes typically have a top surface shape of a truncated cylinder or a parabolic cross section. | 10-08-2009 |
| 20090256203 | Top Gate Thin Film Transistor with Independent Field Control for Off-Current Suppression - A bottom-contacted top gate (TG) thin film transistor (TFT) with independent field control for off-current suppression is provided, along with an associated fabrication method. The method provides a substrate, and forms source and drain regions overlying the substrate, each having a channel interface top surface. A channel is interposed between the source and drain, with source and drain contact regions immediately overlying the source/drain (S/D) interface top surfaces, respectively. A first dielectric layer is formed overlying the source, drain, and channel. A first gate is formed overlying the first dielectric, having a drain sidewall located between the contact regions. A second dielectric layer is formed overlying the first gate and first dielectric. A second gate overlies the second dielectric, located over the drain contact region. | 10-15-2009 |
| 20090294885 | Silicon Nanoparticle Embedded Insulating Film Photodetector - A photodetector is provided with a method for fabricating a semiconductor nanoparticle embedded Si insulating film for photo-detection applications. The method provides a bottom electrode and introduces a semiconductor precursor and hydrogen. A thin-film is deposited overlying the substrate, using a high density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, a semiconductor nanoparticle embedded Si insulating film is formed, where the Si insulating film includes either N or C elements. For example, the Si insulating film may be a non-stoichiometric SiO | 12-03-2009 |
| 20100047476 | Silicon Nanoparticle Precursor - A Si nanoparticle precursor, precursor fabrication process, and precursor deposition process are presented. The method for forming a silicon (Si) nanoparticle precursor provides a plurality of nanoparticle classes, including at least one Si nanoparticle class. The nanoparticles in each nanoparticle class are defined as having a predetermined diameter. A predetermined amount of each nanoparticle class is measured and combined. For example, a first Si nanoparticle class may be provided having a largest diameter and a second Si nanoparticle class having a second-largest diameter equal to about (0.43)×(the largest diameter). As another example, Si nanoparticle classes may foe provided having a diameter ratio of about 77:32:17. | 02-25-2010 |
| 20100102323 | Directionally Annealed Silicon Film Having a (100)-Normal Crystallographical Orientation - A method is provided for forming a directionally crystallized (100)-normal crystallographic orientation silicon (Si) film. The method provides a substrate including Si. An amorphous Si (a-Si) layer is formed overlying the substrate, and a silicon oxide cap layer is formed overlying the a-Si layer. In response to scanning a laser in a first direction along a top surface of the silicon oxide cap layer, the a-Si layer is transformed into a crystalline Si film having a (100)-normal crystallographic orientation, with crystal grains elongated in the first direction. That is, the crystalline Si film has grain boundaries between crystal grains, aligned in parallel with the first direction. | 04-29-2010 |
| 20100117704 | Four-Transistor Schmitt Trigger Inverter with Hysteresis - A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region. | 05-13-2010 |
| 20100151152 | Non-Stoichiometric SiOxNy Optical Filter Fabrication - A non-stoichiometric SiO | 06-17-2010 |
| 20100278475 | Light Emitting Device and Planar Waveguide with Single-Sided Periodically Stacked Interface - Light emitting and waveguide devices with single-sided photonic bandgaps are provided. The light emitting device is formed from a heavily doped silicon (Si) bottom electrode, and a Si-containing dielectric layer embedded Si nanoparticles overlying the bottom electrode. A transparent indium tin oxide (ITO) top electrode overlies the Si-containing dielectric layer, and a photonic bandgap (PBG) Bragg reflector underlies the Si bottom electrode. The PBG Bragg reflector includes at least one periodic bi-layer of films with different refractive indexes. The single-sided photonic bandgap planar waveguide interface is formed from a planar waveguide and a PBG Bragg reflector underlying the planar waveguide. | 11-04-2010 |
| 20110075245 | Full Color Range Interferometric Modulation - A full color range analog controlled interferometric modulation device is provided. The device includes a transparent substrate, and a transparent fixed-position electrically conductive electrode with a bottom surface overlying the substrate. A transparent spacer overlies the fixed-position electrode, and an induced absorber overlies the spacer. An optically reflective electrically conductive moveable membrane overlies the induced absorber. A cavity is formed between the induced absorber and the moveable membrane having a maximum air gap dimension less than the spacer thickness. In one aspect, the distance from the top surface of the fixed-position electrode to a cavity lower surface is at least twice as great as the cavity maximum air gap dimension. In another aspect, at least one anti-reflective coating (ARC) layer is interposed between the substrate and the fixed-position electrode, and at least one ARC layer is interposed between the fixed-position electrode and the spacer. | 03-31-2011 |
| 20110109659 | Plasmonic Electronic Skin - A method is provided for color tuning a plasmonic device with a color tunable electronic skin. A plasmonic electronic skin is used, including a first substrate, a plasmonic structure, an electrically conductive transparent first electrode layer, an electrically conductive transparent second electrode layer, and a polymer-networked liquid crystal (PNLC) layer interposed between the first and second transparent electrode layers. In response to receiving a color tuning voltage, a full visible spectrum incident light, and a PNLC switch voltage, the plasmonic structure generates a first primary color. A primary color exhibits a single wavelength peak with a spectral full width at half magnitudes (FWHMs) in the visible spectrum of light. In response to receiving the PNLC switch voltage between the first and second electrode layers, the PNLC layer passes incident light. | 05-12-2011 |
| 20110109821 | Plasmonic Device Tuned using Liquid Crystal Molecule Dipole Control - A plasmonic display device is provided with liquid crystal dipole molecule control. The device is made from a first set of electrodes including at least one electrically conductive top electrode and at least one electrically conductive bottom electrode capable of generating a first electric field in a first direction. A second set of electrodes, including an electrically conductive right electrode and an electrically conductive left electrode, is capable of generating a second electric field in a second first direction. A dielectric layer overlies the bottom electrode, made from a liquid crystal material with molecules having dipoles responsive to an electric field. A plasmonic layer, including a plurality of discrete plasmonic particles, is interposed between the first and second set of electrodes and in contact with the dielectric layer. In one aspect, the plasmonic layer is embedded in the dielectric layer. | 05-12-2011 |
| 20110109845 | Plasmonic Device Tuned Using Elastic and Refractive Modulation Mechanisms - A plasmonic display device is provided having dual modulation mechanisms. The device has an electrically conductive bottom electrode that may be either transparent or reflective. A dielectric layer overlies the bottom electrode, made from an elastic polymer material having a refractive index responsive to an electric field. An electrically conductive top electrode, either transparent or reflective, overlies the dielectric layer. A plasmonic layer, including a plurality of discrete plasmonic particles, is interposed between the top and bottom electrodes and in contact with the dielectric layer. In one aspect, the plasmonic layer is embedded in the dielectric layer. Alternately, the plasmonic layer overlies the bottom (or top) electrode. Then, the dielectric layer overlies the plasmonic layer particles and exposed regions of the bottom electrode between the first plasmonic layer particles. | 05-12-2011 |
| 20110109854 | Color-Tunable Plasmonic Device with a Partially Modulated Refractive Index - A color-tunable plasmonic device is provided with a partially modulated refractive index. A first dielectric layer overlies a bottom electrode, and has a refractive index non-responsive to an electric field. A second dielectric layer overlies the first dielectric layer, having a refractive index responsive to an electric field. An electrically conductive top electrode overlies the second dielectric layer. A plasmonic layer including a plurality of discrete plasmonic particles is interposed between the top and bottom electrodes. In one aspect, the plasmonic layer is interposed between the first and second dielectric layers. In a second aspect, the plasmonic layer is interposed between the first dielectric layer and the bottom electrode. In a third aspect, a first plasmonic layer is interposed between the first dielectric layer and the bottom electrode, and a second plasmonic layer of discrete plasmonic particles is interposed between the first dielectric layer and the second dielectric layer. | 05-12-2011 |
| 20110109870 | Optical Spectrum Splitting for Black Color Display - A display device is provided for reflecting a black color, as enabled by an optical splitting photonic liquid crystal waveguide. Sets of top and bottom electrodes are formed in a periodic pattern. A first dielectric layer overlies the set of bottom electrodes, made from a liquid crystal (LC) material with molecules having dipoles responsive to an electric field. A plasmonic layer, including a plurality of discrete plasmonic particles, is interposed between the sets of top and bottom electrodes, and is in contact with the first dielectric layer. A voltage potential is applied between the top and bottom electrodes, generating an electric field. Dipole local orientation and non-orientation regions are created in the liquid crystal molecules in response to the electric field, and a wavelength of light outside the visible spectrum is reflected in response to optical spectrum splitting of the incident light. | 05-12-2011 |
| 20110109956 | Plasmonic Device Tuned Using Physical Modulation - A plasmonic display device is provided that uses physical modulation mechanisms. The device is made from an electrically conductive bottom electrode and a first dielectric layer overlying the bottom electrode. The first dielectric layer is a piezoelectric material having an index of expansion responsive to an electric field. An electrically conductive top electrode overlies the first dielectric layer. A first plasmonic layer, including a plurality of discrete plasmonic particles, is interposed between the top and bottom electrodes and in contact with the first dielectric layer. In one aspect, the plasmonic particles are an expandable polymer material covered with a metal coating having a size responsive to an electric field. | 05-12-2011 |
