Patent application number | Description | Published |
20140241021 | INVERTER CONTROL CIRCUIT AND INVERTER CIRCUIT - An inverter control circuit has a quantizer configured to generate a switching signal which changes over switches of a main circuit converting a DC voltage into an AC voltage, and a filter circuit configured to generate a signal having specific transfer characteristic by using a signal correlated with an output voltage of an LC filter which smooths the AC voltage and an instruction signal corresponding to a target value of an output voltage of the main circuit, wherein the quantizer generates the switching signal by quantizing an output signal of the filter circuit. | 08-28-2014 |
20140241270 | WIRELESS COMMUNICATION APPARATUS AND LOGGING SYSTEM - According to an embodiment, a wireless communication apparatus includes a packet generator, a queue unit, a predictor and a scheduler. The packet generator packetizes data. The queue unit temporarily stores a packet to be transmitted. The predictor predicts a transmission time of a first packet to obtain a first time. The scheduler outputs a second packet to the queue unit at a second time earlier than the first time. An interval from a third time when transmission of the second packet is complete until the first time is equal to or shorter than a predetermined period. | 08-28-2014 |
20140288718 | POWER ELECTRONICS DEVICE, COMMUNICATION DEVICE, COOPERATIVE CONTROL METHOD AND COMPUTER READABLE MEDIUM - According to some embodiments, there is provided a power electronics device including: a controlling unit, a determining unit, a confirming unit and a determining unit. The controlling unit performs surveillance/control concerning an input/output of power to a power line with other power electronics devices connected via the power line. The determining unit determines a master device which is a subject of the surveillance/control and a slave device which is controlled by the master device, based on power characteristic information of the other power electronics devices from among the other power electronics devices and the power electronics device. The confirming unit confirms whether the master device and the slave device determined by the determining unit are matched with the master device and the slave device determined by the other power electronics devices. The determining unit permits a start of the surveillance/control when matching is determined by the confirming unit. | 09-25-2014 |
20140288719 | POWER ELECTRONICS DEVICE, POWER CONNECTION INSPECTION METHOD AND NON-TRANSITORY COMPUTER READABLE MEDIUM - According to one embodiment, there is provided a power electronics device including: a connection unit connected to a first power line; a communication unit; at least one unit of an electricity change unit and an electricity detection unit; and a control unit. The communication unit performs communication with other power electronics devices. The electricity change unit changes an energization state of the first power line and the electricity detection unit detects a change in the energization state of the first power line. The control unit specifies a power electronics device connected to the first power line out of the other power electronics devices using the communication unit and said at least one unit of the electricity change unit and the electricity detection unit. | 09-25-2014 |
20150063473 | POWER ELECTRONICS DEVICE, COOPERATIVE CONTROL METHOD AND NON-TRANSITORY COMPUTER READABLE MEDIUM - According to one embodiment, there is provided a power electronics device in which a controlling unit selects a first power electronics device and a second power electronics device from power electronics devices, based on power attribute information and communication attribute information of each power electronics device, and the first power electronics device is a master of power allocation control of electric energy that the power electronics devices connected to one power line of power lines perform input and output on the one power line, and the second power electronics device is a master of output power phase synchronization control of power which the power electronics devices connected to the one power line outputs to the one power line. | 03-05-2015 |
Patent application number | Description | Published |
20090206391 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed on the semiconductor substrate at predetermined intervals, a selecting transistor arranged on each of two sides of each of the plurality of word lines in which a spacing between the selecting transistor and an adjacent one of the word lines is not less than three times a width of each of the word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and selecting transistors, a first cavity portion which is located between each pair of adjacent ones of the word lines and whose upper portion is covered with the interlayer insulating film, a second cavity portion which is formed at a side wall portion of the word line adjacent to each selecting transistor which faces the selecting transistor and whose upper portion is covered with the interlayer insulating film, and a third cavity portion which is formed at a side wall portion of each of the selecting transistors and whose upper portion is covered with the interlayer insulating film. | 08-20-2009 |
20090212352 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity. | 08-27-2009 |
20090218614 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film. | 09-03-2009 |
20100237398 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor storage device includes a semiconductor substrate, a first insulator, a laminated insulator including a second insulator having fixed charges more than those of the first insulator, a single-layer insulator, memory cells between the semiconductor substrate and the first insulator, each memory cells separated from an adjacent memory cell by a cavity portion and including a tunnel insulator, a charge accumulation layer, an insulator, and a control gate electrode, a first selection gate transistor between the semiconductor substrate and the first insulator, a second selection gate transistor between the semiconductor substrate and the first insulator, between one memory cell and the first selection gate transistor, and in contact with the laminated insulator on a first side face on a memory cell side thereof, and a high-voltage peripheral circuit transistor between the semiconductor substrate and the first insulator, and in contact with the single-layer insulator on a side face thereof. | 09-23-2010 |
20110097887 | Semiconductor storage device and method for manufacturing the same - A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film. | 04-28-2011 |
20110147822 | Semiconductor memory device and method for manufacturing the same - A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity. | 06-23-2011 |
20120012916 | Stacked gate nonvolatile semiconductor memory and method for manufacturing the same - A stacked gate nonvolatile semiconductor memory includes at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate. The memory cell transistor includes a floating gate made of a semiconductor material below an interlayer insulating layer and a control gate made of a silicide above the interlayer insulating layer. The selective gate transistor includes a semiconductor layer made of the semiconductor material, a silicide layer made of the silicide and a conductive layer made of a conductive material not subject to silicide process which is formed through the interlayer insulating film so as to electrically connect the semiconductor layer and the silicide layer. | 01-19-2012 |
20120217464 | NONVOLATILE STORAGE DEVICE - A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode. | 08-30-2012 |
20130020629 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a plurality of word lines formed on a semiconductor substrate at predetermined intervals, selecting transistors arranged on at least one side of the plurality of word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and the selecting transistors, a first air gap located between each pair of adjacent ones of the word lines and covered by the interlayer insulating film, a second air gap located at a first side wall portion of a word line adjacent to the selecting transistors covered by the interlayer insulating film, the first side wall portion facing the selecting transistors, and a third air gap located at a second side wall portion of each of the selecting transistors and covered by the interlayer insulating film. The first, second, and third air gaps are filled with air. | 01-24-2013 |
20130234224 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD FOR THE SAME - According to one embodiment, a semiconductor storage device comprises a memory cell transistor including a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film and a control gate which are sequentially formed on a substrate, and a select transistor including a fourth insulating film, a first electrode layer, a fifth insulating film, a second electrode layer, a sixth insulating film and a third electrode layer which are sequentially formed on the substrate. Openings are provided in at least parts of the fifth insulating film and the sixth insulating film. The first electrode layer, the second electrode layer and the third electrode layer are electrically connected via the openings. | 09-12-2013 |
20140042517 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - In accordance with an embodiment, a semiconductor memory device includes a substrate and a plurality of memory cells. The substrate includes a semiconductor layer on a surface thereof. Each the memory cell includes a laminated body with a tunnel insulating film and a floating gate on the tunnel insulating film, a gate insulating film on the laminated body, and a control gate on the gate insulating film. The laminated body is sequentially laminated on the semiconductor layer in a direction vertical to the surface of the substrate for N (a natural number equal to or above 2) times. A dimension of the floating gate in the lowermost layer is at least partially smaller than a dimension of the floating gate in each of second and subsequent layers in at least one of a first direction parallel to the surface of the substrate and a second direction crossing the first direction. | 02-13-2014 |
20140048864 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - In accordance with an embodiment, a semiconductor memory device includes a substrate with a semiconductor layer and memory cells on the semiconductor layer. Each memory cell includes a laminated body on the semiconductor layer, a gate insulating film on the laminated body, and a control gate on the gate insulating film. The laminated body includes a tunnel insulating film and a floating gate subsequently laminated in a direction vertical to a front surface of the substrate for N (a natural number equal to or above 2) times. A dimension of a top face of any floating gate in a second or subsequent layer is smaller than a dimension of a bottom surface of the floating gate in the lowermost layer in at least one of a first direction parallel to the front surface of the substrate and a second direction crossing the first direction. | 02-20-2014 |