| Patent application number | Description | Published |
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| 20080273400 | FAST ERASABLE NON-VOLATILE MEMORY - A method writes data in a non-volatile memory comprising a main memory area comprising target locations, and an auxiliary memory area comprising auxiliary locations. The method comprises a write-erase cycle comprising: reading an initial set of data in a source location located in the main or auxiliary memory area; inserting the piece of data to be written into the initial set of data, to obtain an updated set of data, partially erasing a first group of auxiliary locations and a group of target locations designated by locations of a second group of auxiliary locations, and writing, in an erased auxiliary location of a third group of auxiliary locations, the updated set of data and the address of the target location. The method is particularly applicable to FLASH memories. | 11-06-2008 |
| 20080301356 | FAST WRITING NON-VOLATILE MEMORY - A method writes data in a non-volatile memory comprising memory cells that are erased before being written. The method comprises the steps of providing a main non-volatile memory area comprising target pages, providing an auxiliary non-volatile memory area comprising auxiliary pages, providing a look-up table to associate to an address of invalid target page an address of valid auxiliary page, and, in response to a command for writing a piece of data in a target page writing the piece of data as well as the address of the target page in a first erased auxiliary page, invalidating the target page, and updating the look-up table. | 12-04-2008 |
| 20080301357 | NON-VOLATILE MEMORY WITH AUXILIARY ROTATING SECTORS - A method writes data in a non-volatile memory. The method provides, in the memory, a non-volatile main memory area comprising target pages, a non-volatile auxiliary memory area comprising auxiliary pages, and, in the auxiliary memory area: a current sector comprising erased auxiliary pages usable to write data, a save sector comprising auxiliary pages comprising data linked to target pages to be erased or being erased, a transfer sector comprising auxiliary pages including data to be transferred to erased target pages, and an unavailable sector comprising auxiliary pages to be erased or being erased. The method can be applied in particular to FLASH memories. | 12-04-2008 |
| 20090284304 | CIRCUIT FOR GENERATING A TEMPERATURE-COMPENSATED VOLTAGE REFERENCE, IN PARTICULAR FOR APPLICATIONS WITH SUPPLY VOLTAGES LOWER THAN 1V - An embodiment of a circuit is described for the generation of a temperature-compensated voltage reference of the type comprising at least one generator circuit of a band-gap voltage, inserted between a first and a second voltage reference and including an operational amplifier, having in turn a first and a second input terminal connected to an input stage connected to these first and second input terminal and comprising at least one pair of a first and a second bipolar transistor for the generation of a first voltage component proportional to the temperature. The circuit also comprises the control block connected to the generator circuit of a band-gap voltage in correspondence with at least one first control node which is supplied with a biasing voltage value comprising at least one voltage component which increases with the temperature for compensating the variations of the base-emitter voltage of the first and second bipolar transistors and ensure the turn-on of a pair of input transistors of the operational amplifier. The circuit has an output terminal suitable for supplying a temperature-compensated voltage value obtained by the sum of the first voltage component proportional to the temperature and of a second component inversely proportional to the temperature. | 11-19-2009 |
| 20110068179 | METHOD FOR BIASING AN EEPROM NON-VOLATILE MEMORY ARRAY AND CORRESPONDING EEPROM NON-VOLATILE MEMORY DEVICE - Described herein is a method for biasing an EEPROM array formed by memory cells arranged in rows and columns, each operatively coupled to a first switch and to a second switch and having a first current-conduction terminal selectively connectable to a bitline through the first switch and a control terminal selectively connectable to a gate-control line through the second switch, wherein associated to each row are a first wordline and a second wordline, connected to the control terminals of the first switches and, respectively, of the second switches operatively coupled to the memory cells of the same row. The method envisages selecting at least one memory cell for a given memory operation, biasing the first wordline and the second wordline of the row associated thereto, and in particular biasing the first and second wordlines with voltages different from one another and having values that are higher than an internal supply voltage and are a function of the given memory operation. | 03-24-2011 |
| 20110068857 | LATCH CHARGE PUMP WITH EQUALIZATION CIRCUIT - A charge pump including first and a second charge-pump stages electrically coupled, four pump capacitors connected between two enable terminals and four internal nodes, two pump transistors connected to the pump capacitors and to the internal nodes, and having respective control terminals, two biasing capacitors, connected between the control terminals and the enable terminals, and an equalization circuit connected between the control terminals and structured to limit the voltage between the control terminals within a first range of values. | 03-24-2011 |
| 20110069554 | SENSE-AMPLIFIER CIRCUIT FOR NON-VOLATILE MEMORIES THAT OPERATES AT LOW SUPPLY VOLTAGES - A sense-amplifier circuit includes: a comparison stage that compares a cell current that flows in a memory cell and through an associated bitline, with a reference current, for supplying an output signal indicating the state of the memory cell; and a precharging stage, which supplies, during a precharging step prior to the comparison step, a precharging current to the bitline so as to charge a capacitance thereof. The comparison stage includes a first comparison transistor and by a second comparison transistor, which are coupled in current-mirror configuration respectively to a first differential output and to a second differential output, through which a biasing current flows. The precharging stage diverts, during the precharging step, the biasing current towards the bitline as precharging current, and allows, during the comparison step, passage of part of the biasing current towards the first differential output, enabling operation of the current mirror. | 03-24-2011 |
| 20110069562 | LOW CONSUMPTION VOLTAGE REGULATOR FOR A HIGH VOLTAGE CHARGE PUMP, VOLTAGE REGULATION METHOD, AND MEMORY DEVICE PROVIDED WITH THE VOLTAGE REGULATOR - A voltage regulator for a regulated voltage generator configured to generate an operating voltage and including a variable comparison voltage generator, a comparison voltage, a partition branch including a plurality of active devices of a resistive type to receive the operating voltage and supply an intermediate voltage correlated to the operating voltage, and a comparator, to receive the comparison voltage and the intermediate voltage and supply a regulation signal for the regulated-voltage generator. | 03-24-2011 |
