| Patent application number | Description | Published |
|---|
| 20080224256 | SEMICONDUCTOR-ON-INSULATOR(SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX) - A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer | 09-18-2008 |
| 20080242041 | Selective Deposition of Germanium Spacers on Nitride - A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface. | 10-02-2008 |
| 20090007051 | SELECTABLE DEVICE OPTIONS FOR CHARACTERIZING SEMICONDUCTOR DEVICES - A system, method and program product that allows multiple devices to be placed between pads such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system is disclosed for implementing a testsite for characterizing devices in an integrated circuit technology, and includes: a system for designing a plurality of device options for a set of chip pads; a system for designing a pseudo wiring layout for each of the plurality of device options; a system for selecting one of the device options; a system for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and a system for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option. | 01-01-2009 |
| 20090269926 | POLYGRAIN ENGINEERING BY ADDING IMPURITIES IN THE GAS PHASE DURING CHEMICAL VAPOR DEPOSITION OF POLYSILICON - A method of forming at least one gate conductor of a complementary metal oxide semiconductor performs a chemical vapor deposition process of polysilicon over a surface where a polysilicon gate is to be located. This deposition can be performed through a mask to form gate structures directly, or a later patterning process can pattern the polysilicon into gate structures. During the chemical vapor deposition process, the method adds impurities in the chemical vapor deposition process to optimize the grain size of the polysilicon according to a number of different methods. | 10-29-2009 |
| 20090302386 | SOI TRANSISTOR HAVING A CARRIER RECOMBINATION STRUCTURE IN A BODY - A top semiconductor layer is formed with two different thicknesses such that a step is formed underneath a body region of a semiconductor-on-insulator (SOI) field effect transistor at the interface between a top semiconductor layer and an underlying buried insulator layer. The interface and the accompanying interfacial defects in the body region provide recombination centers, which increase the recombination rate between the holes and electrons in the body region. Optionally, a spacer portion, comprising a material that functions as recombination centers, is formed on sidewalls of the step to provide an enhanced recombination rate between holes and electrons in the body region, which increases the bipolar breakdown voltage of a SOI field effect transistor. | 12-10-2009 |
| 20090315138 | METHOD AND STRUCTURE FOR SOI BODY CONTACT FET WITH REDUCED PARASITIC CAPACITANCE - In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region. | 12-24-2009 |
| 20110034000 | SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE - A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface. | 02-10-2011 |
