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Angyal
Matthew Angyal, Stormville, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090026587 | GRADIENT DEPOSITION OF LOW-K CVD MATERIALS - A dielectric layer for a semiconductor device having a low overall dielectric constant, good adhesion to the semiconductor substrate, and good resistance to cracking due to thermal cycling. The dielectric layer is made by a process involving continuous variation of dielectric material deposition conditions to provide a dielectric layer having a gradient of dielectric constant. | 01-29-2009 |
| 20090031260 | Method, Computer Program and System Providing for Semiconductor Processes Optimization - A method, computer program and system for the optimization of semiconductor process parameters given a pre-specified set of targets and constraints on electrical performance metrics are disclosed. Semiconductor process engineers who are not expert in the art of electrical analysis or mathematical optimization can readily use the method of this invention in optimizing semiconductor process parameters. Accommodates the differences in design styles, metal layer routing, and electrical metrics using priority schedules that are easy to input and understand. Enables the exploration of the process parameter space using primitive process tolerances and accurate electrical information provided by field solvers and circuit analysis programs. | 01-29-2009 |
| 20110037143 | Semiconductor Device Using An Aluminum Interconnect To Form Through-Silicon Vias - An aluminum lateral interconnect of a Back End of the Line (BEOL) is used to define the x and y dimensions of a through-silicon via in a semiconductor chip formed in a silicon substrate. The TSV includes one or more aluminum annulus formed on a surface of the substrate, and a deep trench in the substrate having a diameter that is determined by the diameter of the aluminum annulus. The annulus can also be provided with a conductive strap upon which a capacitor can be formed. The strap can also be used to provide a connection of the TV to other BEOL interconnects. | 02-17-2011 |
Matthew S. Angyal, Hopewell Junction, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100200958 | PEDESTAL GUARD RING HAVING CONTINUOUS M1 METAL BARRIER CONNECTED TO CRACK STOP - A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip. A continuous metal ring extending continuously in the first lateral directions can surround the active portion of the chip, such metal ring connecting the GR contact ring with the first crack stop ring such that the metal line and the GR contact ring form a continuous seal preventing mobile ions from moving between the peripheral and active portions of the chip. | 08-12-2010 |
| 20100200960 | DEEP TRENCH CRACKSTOPS UNDER CONTACTS - Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns. | 08-12-2010 |
Matthew Stephen Angyal, Stormville, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080221849 | Method, Apparatus And Computer Program Product For Creating Electric Circuit Models Of Semiconductor Circuits From Fabrication Process Parameters - Disclosed herein are methods and apparatus that automatically generate an electric circuit model from process parameters used to specify a semiconductor fabrication procedure, wherein at least one of the process parameters is specified as a statistical distribution. The methods and apparatus convert the process parameters into an electric circuit model. The electric circuit model is specified in terms of electric parameters, wherein at least one of the electric parameters is specified in terms of a statistical distribution. The methods and apparatus thus allow a process engineer whose expertise may not extend to state-of-the-art circuit modeling to develop insight into the effect of process parameter selection on the performance of the resulting electric circuit. The resulting insight is further enhanced since at least one of the electric parameters is specified in terms of a statistical distribution. | 09-11-2008 |