| Patent application number | Description | Published |
|---|
| 20080303027 | Semiconductor Device Made by the Method of Producing Hybrid Orientnation (100) Strained Silicon with (110) Silicon - There is provided a method of manufacturing a semiconductor device. In one aspect, the method includes providing a strained silicon layer having a crystal orientation located over a semiconductor substrate having a different crystal orientation. A mask is placed over a portion of the strained silicon layer to leave an exposed portion of the strained silicon layer. The exposed portion of the strained silicon layer is amorphized and re-crystallized to a crystal structure having an orientation the same as the semiconductor substrate. | 12-11-2008 |
| 20090057816 | METHOD TO REDUCE RESIDUAL STI CORNER DEFECTS GENERATED DURING SPE IN THE FABRICATION OF NANO-SCALE CMOS TRANSISTORS USING DSB SUBSTRATE AND HOT TECHNOLOGY - A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing. | 03-05-2009 |
| 20090159932 | INTEGRATION SCHEME FOR REDUCING BORDER REGION MORPPHOLOGY IN HYBRID ORIENTATION TECHNOLOGY (HOT) USING DIRECT SILICON BONDED (DSB) SUBSTRATES - Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells appropriate for the technology node. This invention provides a method of forming an integrated circuit (IC) substrate containing regions with two different silicon crystal lattice orientations. Starting with a (110) direct silicon bonded (DSB) layer on a (100) substrate, regions in the DSB layer are amorphized and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Lateral templating by the DSB layer is reduced by amorphization of the upper portion of the (110) regions through a partially absorbing amorphization hard mask. Boundary morphology is less than 40 nanometers wide. An integrated circuit formed with the inventive method is also disclosed. | 06-25-2009 |
| 20090159933 | INTEGRATION SCHEME FOR CHANGING CRYSTAL ORIENTATION IN HYBRID ORIENTATION TECHNOLOGY (HOT) USING DIRECT SILICON BONDED (DSB) SUBSTRATES - Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming ( | 06-25-2009 |
| 20100032727 | BORDER REGION DEFECT REDUCTION IN HYBRID ORIENTATION TECHNOLOGY (HOT) DIRECT SILICON BONDED (DSB) SUBSTRATES - Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed. | 02-11-2010 |
| 20100216286 | USE OF IN-SITU HCL ETCH TO ELIMINATE BY OXIDATION RECRYSTALLIZATION BORDER DEFECTS GENERATED DURING SOLID PHASE EPITAXY (SPE) IN THE FABRICATION OF NANO-SCALE CMOS TRANSISTORS USING DIRECT SILICON BOND SUBSTRATE (DSB) AND HYBRID ORIENTATION TECHNOLOGY (HOT) - A method for reducing defects at an interface between a amorphized, recrystallized cleaved wafer layer and an unamorphized cleaved wafer layer can comprise an anneal and an exposure to hydrochloric acid. The anneal and acid exposure can be performed within an epitaxial reactor chamber to minimize wafer transport. | 08-26-2010 |
| 20100279481 | CONTROL OF DOPANT DIFFUSION FROM BURIED LAYERS IN BIPOLAR INTEGRATED CIRCUITS - An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors ( | 11-04-2010 |
| 20100304547 | REDUCTION OF STI CORNER DEFECTS DURING SPE IN SEMICONDCUTOR DEVICE FABRICATION USING DSB SUBSTRATE AND HOT TECHNOLOGY - A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing. | 12-02-2010 |
| 20110108893 | INTEGRATION SCHEME FOR CHANGING CRYSTAL ORIENTATION IN HYBRID ORIENTATION TECHNOLOGY (HOT) USING DIRECT SILICON BONDED (DSB) SUBSTRATES - Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and ( | 05-12-2011 |
| 20110151651 | METHOD FOR FORMING INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS - A method of forming an integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations. | 06-23-2011 |
