| Patent application number | Description | Published |
|---|
| 20080203427 | SEMICONDUCTOR DEVICE HAVING A STRAINED SEMICONDUCTOR ALLOY CONCENTRATION PROFILE - A new technique enables providing a stress-inducing alloy having a highly stress-inducing region and a region which is processable by standard processing steps suitable for use in a commercial high volume semiconductor device manufacturing environment. The regions may be formed by a growth process with a varying composition of the growing material or by other methods such as ion implantation. The highly stress-inducing region near the channel region of a transistor may be covered with an appropriate cover. | 08-28-2008 |
| 20080203486 | METHOD FOR DIFFERENTIAL SPACER REMOVAL BY WET CHEMICAL ETCH PROCESS AND DEVICE WITH DIFFERENTIAL SPACER STRUCTURE - By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions. | 08-28-2008 |
| 20080237712 | SOI TRANSISTOR HAVING DRAIN AND SOURCE REGIONS OF REDUCED LENGTH AND A STRESSED DIELECTRIC MATERIAL ADJACENT THERETO - By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake. | 10-02-2008 |
| 20080237723 | METHOD FOR CREATING TENSILE STRAIN BY REPEATEDLY APPLIED STRESS MEMORIZATION TECHNIQUES - By introducing additional strain-inducing mechanisms on the basis of stress memorization techniques, the performance of NMOS transistors may be significantly increased, thereby reducing the imbalance between PMOS transistors and NMOS transistors. By amorphizing and re-crystallizing the respective material in the presence of a mask layer at various stages of the manufacturing process, a drive current improvement of up to approximately 27% has been observed, with the potential for further performance gain. | 10-02-2008 |
| 20080268585 | SOI DEVICE HAVING A SUBSTRATE DIODE WITH PROCESS TOLERANT CONFIGURATION AND METHOD OF FORMING THE SOI DEVICE - A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices. | 10-30-2008 |
| 20080268597 | TECHNIQUE FOR ENHANCING DOPANT ACTIVATION BY USING MULTIPLE SEQUENTIAL ADVANCED LASER/FLASH ANNEAL PROCESSES - By performing multiple radiation-based anneal processes on the basis of less critical process parameters, the overall risk for creating anneal-induced damage, such as melting of gate portions, may be substantially avoided while nevertheless the respective degree of dopant activation may be enhanced for each individual anneal process. Consequently, the sheet resistance of advanced transistor devices may be reduced with a decreasing number of sequential anneal processes. | 10-30-2008 |
| 20080296693 | ENHANCED TRANSISTOR PERFORMANCE OF N-CHANNEL TRANSISTORS BY USING AN ADDITIONAL LAYER ABOVE A DUAL STRESS LINER IN A SEMICONDUCTOR DEVICE - By forming an additional dielectric material, such as silicon nitride, after patterning dielectric liners of different intrinsic stress, a significant increase of performance of N-channel transistors may be obtained while substantially not contributing to a performance loss of the P-channel transistor. | 12-04-2008 |
| 20090001371 | BLOCKING PRE-AMORPHIZATION OF A GATE ELECTRODE OF A TRANSISTOR - A technique is presented which provides for a selective pre-amorphization of source/drain regions of a transistor while preventing pre-amorphization of a gate electrode of the transistor. Illustrative embodiments include the formation of a pre-amorphization implant blocking material over the gate electrode. Further illustrative embodiments include inducing a strain in a channel region by use of various stressors. | 01-01-2009 |
| 20090057769 | CMOS DEVICE HAVING GATE INSULATION LAYERS OF DIFFERENT TYPE AND THICKNESS AND A METHOD OF FORMING THE SAME - In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level. | 03-05-2009 |
| 20090057809 | STRESS TRANSFER IN AN INTERLAYER DIELECTRIC BY PROVIDING A STRESSED DIELECTRIC LAYER ABOVE A STRESS-NEUTRAL DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE - By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor. | 03-05-2009 |
| 20090057813 | METHOD FOR SELF-ALIGNED REMOVAL OF A HIGH-K GATE DIELECTRIC ABOVE AN STI REGION - By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material. | 03-05-2009 |
| 20090087974 | METHOD OF FORMING HIGH-K GATE ELECTRODE STRUCTURES AFTER TRANSISTOR FABRICATION - A sophisticated high-k metal gate electrode structure may be formed after the deposition of a first part of an interlayer dielectric material, thereby providing a high degree of process compatibility with conventional CMOS techniques. Thus, sophisticated strain-inducing mechanisms may be readily implemented in the overall process flow, while nevertheless avoiding any high temperature processes during the formation of the sophisticated high-k dielectric gate stack. | 04-02-2009 |
| 20090108361 | TENSILE STRAIN SOURCE USING SILICON/GERMANIUM IN GLOBALLY STRAINED SILICON - By embedding a silicon/germanium mixture in a silicon layer of high tensile strain, a moderately high degree of tensile strain may be maintained in the silicon/germanium mixture, thereby enabling increased performance of N-channel transistors on the basis of silicon/germanium material. | 04-30-2009 |
| 20090142900 | METHOD FOR CREATING TENSILE STRAIN BY SELECTIVELY APPLYING STRESS MEMORIZATION TECHNIQUES TO NMOS TRANSISTORS - By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an appropriate material layer which may not to be patterned prior to the anneal process, thereby avoiding additional lithography and masking steps. | 06-04-2009 |
| 20090166618 | TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS - By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished. | 07-02-2009 |
| 20090218633 | CMOS DEVICE COMPRISING AN NMOS TRANSISTOR WITH RECESSED DRAIN AND SOURCE AREAS AND A PMOS TRANSISTOR HAVING A SILICON/GERMANIUM MATERIAL IN THE DRAIN AND SOURCE AREAS - A recessed transistor configuration may be provided selectively for one type of transistor, such as N-channel transistors, thereby enhancing strain-inducing efficiency and series resistance, while a substantially planar configuration or raised drain and source configuration may be provided for other transistors, such as P-channel transistors, which may also include a strained semiconductor alloy, while nevertheless providing a high degree of compatibility with CMOS techniques. For this purpose, an appropriate masking regime may be provided to efficiently cover the gate electrode of one transistor type during the formation of the corresponding recesses, while completely covering the other type of transistor. | 09-03-2009 |
| 20090246926 | METHOD FOR CREATING TENSILE STRAIN BY APPLYING STRESS MEMORIZATION TECHNIQUES AT CLOSE PROXIMITY TO THE GATE ELECTRODE - After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch stop layer so that a rigid material layer may be positioned more closely to the gate electrode, thereby enhancing the overall strain-inducing mechanism during a subsequent anneal process in the presence of the material layer and providing an enhanced stress memorization technique (SMT). In some illustrative embodiments, a selective SMT approach may be provided. | 10-01-2009 |
| 20090294860 | IN SITU FORMED DRAIN AND SOURCE REGIONS IN A SILICON/GERMANIUM CONTAINING TRANSISTOR DEVICE - By repeatedly applying a process sequence comprising an etch process and a selective epitaxial growth process during the formation of drain and source areas in a transistor device, highly complex dopant profiles may be generated on the basis of in situ doping. Further-more, a strain material may be provided while stress relaxation mechanisms may be reduced due to the absence of any implantation processes. | 12-03-2009 |
| 20090321836 | DOUBLE GATE AND TRI-GATE TRANSISTOR FORMED ON A BULK SUBSTRATE AND METHOD FOR FORMING THE TRANSISTOR - Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas, the fins and isolation structures in a self-aligned manner within a bulk semiconductor material. After defining the basic fin structures, highly efficient manufacturing techniques of planar transistor configurations may be used, thereby even further enhancing overall performance of the three-dimensional transistor configurations. | 12-31-2009 |
| 20090321837 | CONTACT TRENCHES FOR ENHANCING STRESS TRANSFER IN CLOSELY SPACED TRANSISTORS - Scalability of a strain-inducing mechanism on the basis of a stressed dielectric overlayer may be enhanced by forming a single stress-inducing layer in combination with contact trenches, which may shield a significant amount of a non-desired stress component in the complementary transistor, while also providing a strain component in the transistor width direction when the contact material may be provided with a desired internal stress level. | 12-31-2009 |
| 20090321841 | CMOS DEVICE COMPRISING MOS TRANSISTORS WITH RECESSED DRAIN AND SOURCE AREAS AND NON-CONFORMAL METAL SILICIDE REGIONS - A non-conformal metal silicide in a transistor of recessed drain and source configuration may provide enhanced efficiency with respect to strain-inducing mechanisms, drain/source resistance and the like. For this purpose, in some cases, an amorphizing implantation process may be performed prior to the silicidation process, while in other cases an anisotropic deposition of the refractory metal may be used. | 12-31-2009 |
| 20090321843 | CMOS DEVICE COMPRISING MOS TRANSISTORS WITH RECESSED DRAIN AND SOURCE AREAS AND A SI/GE MATERIAL IN THE DRAIN AND SOURCE AREAS OF THE PMOS TRANSISTOR - The present disclosure relates to semiconductor devices and a process sequence in which a semiconductor alloy, such as silicon/germanium, may be formed in an early manufacturing stage, wherein other performance-increasing mechanisms, such as a recessed drain and source configuration, possibly in combination with high-k dielectrics and metal gates, may be incorporated in an efficient manner while still maintaining a high degree of compatibility with conventional process techniques. | 12-31-2009 |
| 20100025779 | SHALLOW PN JUNCTION FORMED BY IN SITU DOPING DURING SELECTIVE GROWTH OF AN EMBEDDED SEMICONDUCTOR ALLOY BY A CYCLIC GROWTH/ETCH DEPOSITION PROCESS - A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior. | 02-04-2010 |
| 20100055867 | STRUCTURED STRAINED SUBSTRATE FOR FORMING STRAINED TRANSISTORS WITH REDUCED THICKNESS OF ACTIVE LAYER - In a strained SOI semiconductor layer, the stress relaxation which may typically occur during the patterning of trench isolation structures may be reduced by selecting an appropriate reduced target height of the active regions, thereby enabling the formation of transistor elements on the active region of reduced height, which may still include a significant amount of the initial strain component. The active regions of reduced height may be advantageously used for forming fully depleted field effect transistors. | 03-04-2010 |
| 20100078645 | SEMICONDUCTOR DEVICE COMPRISING A BURIED POLY RESISTOR - An embedded or buried resistive structure may be formed by amorphizing a semiconductor material and subsequently re-crystallizing the same in a polycrystalline state, thereby providing a high degree of compatibility with conventional polycrystalline resistors, such as polysilicon resistors, while avoiding the deposition of a dedicated polycrystalline material. Hence, polycrystalline resistors may be advantageously combined with sophisticated transistor architectures based on non-silicon gate electrode materials, while also providing high performance of the resistors with respect to the parasitic capacitance. | 04-01-2010 |
| 20100078689 | TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING REDUCED OFFSET TO THE CHANNEL REGION - A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency. | 04-01-2010 |
| 20100078691 | TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED ACROSS-SUBSTRATE UNIFORMITY - In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystallographic orientations. In one embodiment, TMAH may be used which exhibits, in addition to the anisotropic etch behavior, a high etch selectivity with respect to silicon dioxide, thereby enabling extremely thin etch stop layers which additionally provide the possibility of further reducing the offset from the channel region while not unduly contributing to overall process variability. | 04-01-2010 |
| 20100090321 | HIGH-K ETCH STOP LAYER OF REDUCED THICKNESS FOR PATTERNING A DIELECTRIC MATERIAL DURING FABRICATION OF TRANSISTORS - By providing a high-k dielectric etch stop material as an etch stop layer for patterning an interlayer dielectric material, enhanced performance and higher flexibility may be achieved since, for instance, an increased amount of highly stressed dielectric material may be positioned more closely to the respective transistors due to the reduced thickness of the high-k dielectric etch stop material. | 04-15-2010 |
| 20100109091 | RECESSED DRAIN AND SOURCE AREAS IN COMBINATION WITH ADVANCED SILICIDE FORMATION IN TRANSISTORS - During the manufacturing process for forming sophisticated transistor elements, the gate height may be reduced and a recessed drain and source configuration may be obtained in a common etch sequence prior to forming respective metal silicide regions. Since the corresponding sidewall spacer structure may be maintained during the etch sequence, controllability and uniformity of the silicidation process in the gate electrode may be enhanced, thereby obtaining a reduced degree of threshold variability. Furthermore, the recessed drain and source configuration may provide reduced overall series resistance and enhanced stress transfer efficiency. | 05-06-2010 |
| 20100133615 | MULTIPLE GATE TRANSISTOR HAVING FINS WITH A LENGTH DEFINED BY THE GATE ELECTRODE - The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process. | 06-03-2010 |
| 20100155727 | TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS - By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished. | 06-24-2010 |
| 20100155850 | TECHNIQUE FOR PROVIDING STRESS SOURCES IN TRANSISTORS IN CLOSE PROXIMITY TO A CHANNEL REGION BY RECESSING DRAIN AND SOURCE REGIONS - By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism. | 06-24-2010 |
| 20100181619 | METHOD OF FORMING A FIELD EFFECT TRANSISTOR - A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained. | 07-22-2010 |
| 20100187629 | TENSILE STRAIN SOURCE USING SILICON/GERMANIUM IN GLOBALLY STRAINED SILICON - By embedding a silicon/germanium mixture in a silicon layer of high tensile strain, a moderately high degree of tensile strain may be maintained in the silicon/germanium mixture, thereby enabling increased performance of N-channel transistors on the basis of silicon/germanium material. In other regions, the germanium concentration may be varied to provide different levels of tensile or compressive strain. | 07-29-2010 |
| 20100193860 | SHORT CHANNEL TRANSISTOR WITH REDUCED LENGTH VARIATION BY USING AMORPHOUS ELECTRODE MATERIAL DURING IMPLANTATION - In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions and halo regions. | 08-05-2010 |
| 20100193866 | GRADED WELL IMPLANTATION FOR ASYMMETRIC TRANSISTORS HAVING REDUCED GATE ELECTRODE PITCHES - In sophisticated semiconductor devices, an asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose, a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration. | 08-05-2010 |
| 20100252866 | TRANSISTOR HAVING A CHANNEL WITH TENSILE STRAIN AND ORIENTED ALONG A CRYSTALLOGRAPHIC ORIENTATION WITH INCREASED CHARGE CARRIER MOBILITY - By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the <100> direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four. | 10-07-2010 |
| 20100289080 | SEMICONDUCTOR DEVICE COMPRISING METAL GATES AND A SILICON CONTAINING RESISTOR FORMED ON AN ISOLATION STRUCTURE - In a semiconductor device comprising sophisticated high-k metal gate structures formed in accordance with a replacement gate approach, semiconductor-based resistors may be formed above isolation structures substantially without being influenced by the replacement gate approach. Consequently, enhanced area efficiency may be achieved compared to conventional strategies, in which the resistive structures may have to be provided on the basis of a gate electrode metal, while, nevertheless, a low parasitic capacitance may be accomplished due to providing the resistive structures above the isolation structure. | 11-18-2010 |
| 20100301416 | STRAIN TRANSFORMATION IN BIAXIALLY STRAINED SOI SUBSTRATES FOR PERFORMANCE ENHANCEMENT OF P-CHANNEL AND N-CHANNEL TRANSISTORS - In advanced SOI devices, a high tensile strain component may be achieved on the basis of a globally strained semiconductor layer, while at the same time a certain compressive strain may be induced in P-channel transistors by appropriately selecting a height-to-length aspect ratio of the corresponding active regions. It has been recognized that the finally obtained strain distribution in the active regions is strongly dependent on the aspect ratio of the active regions. Thus, by selecting a moderately low height-to-length aspect ratio for N-channel transistors, a significant fraction of the initial tensile strain component may be preserved. On the other hand, a moderately high height-to-length aspect ratio for the P-channel transistor may result in a compressive strain component in a central surface region of the active region. | 12-02-2010 |
| 20110049642 | WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS INCLUDING GATE DIELECTRICS OF DIFFERENT THICKNESS - In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species within the high-k dielectric material with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species, the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors having a different thickness gate dielectric material may be avoided. | 03-03-2011 |
| 20110073956 | FORMING SEMICONDUCTOR RESISTORS IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES BY INCREASING ETCH RESISTIVITY OF THE RESISTORS - In a replacement gate approach, the polysilicon material may be efficiently removed during a wet chemical etch process, while the semiconductor material in the resistive structures may be substantially preserved. For this purpose, a species such as xenon may be incorporated into the semiconductor material of the resistive structure, thereby imparting a significantly increased etch resistivity to the semiconductor material. The xenon may be incorporated at any appropriate manufacturing stage. | 03-31-2011 |
| 20110101427 | TRANSISTOR INCLUDING A HIGH-K METAL GATE ELECTRODE STRUCTURE FORMED PRIOR TO DRAIN/SOURCE REGIONS ON THE BASIS OF A SUPERIOR IMPLANTATION MASKING EFFECT - When forming a sophisticated high-k metal gate stack in an early manufacturing stage, the dielectric cap layer may be efficiently removed without unduly affecting the drain and source extension regions. To this end, a specifically designed sidewall spacer structure may be used, such as a silicon dioxide spacer element in combination with a silicon nitride etch stop liner. The spacer structure may thus enable the removal of the dielectric cap layer while still maintaining the functions of an implantation mask and a silicidation mask during the further processing. | 05-05-2011 |
| 20110127618 | PERFORMANCE ENHANCEMENT IN PFET TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY INCREASING DOPANT CONFINEMENT - In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events. | 06-02-2011 |
| 20110156162 | SEMICONDUCTOR RESISTORS FORMED AT A LOWER HEIGHT LEVEL IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES - In sophisticated semiconductor devices comprising high-k metal gate electrode structures formed on the basis of a replacement gate approach, semiconductor-based resistors may be provided without contributing to undue process complexity in that the resistor region is recessed prior to depositing the semiconductor material of the gate electrode structure. Due to the difference in height level, a reliable protective dielectric material layer is preserved above the resistor structure upon exposing the semiconductor material of the gate electrode structure and removing the same on the basis of selective etch recipes. Consequently, well-established semiconductor materials, such as polysilicon, may be used for the resistive structures in complex semiconductor devices, substantially without affecting the overall process sequence for forming the sophisticated replacement gate electrode structures. | 06-30-2011 |
| 20110159654 | ENHANCED CONFINEMENT OF HIGH-K METAL GATE ELECTRODE STRUCTURES BY REDUCING MATERIAL EROSION OF A DIELECTRIC CAP LAYER UPON FORMING A STRAIN-INDUCING SEMICONDUCTOR ALLOY - When forming the strain-inducing semiconductor alloy in one type of transistor of a sophisticated semiconductor device, superior thickness uniformity of a dielectric cap material of the gate electrode structures may be achieved by forming encapsulating spacer elements on each gate electrode structure and providing an additional hard mask material. Consequently, in particular, in sophisticated replacement gate approaches, the dielectric cap material may be efficiently removed in a later manufacturing stage, thereby avoiding any irregularities upon replacing the semiconductor material by an electrode metal. | 06-30-2011 |
| 20110159657 | ENHANCED INTEGRITY OF A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL SPACER FOR CAP REMOVAL - In a process strategy for forming sophisticated high-k metal gate electrode structures in an early manufacturing phase, the dielectric cap material may be removed on the basis of a protective spacer element, thereby ensuring integrity of a silicon nitride sidewall spacer structure, which may preserve integrity of sensitive gate materials and may also determine the lateral offset of a strain-inducing semiconductor material. | 06-30-2011 |
