Patent application number | Description | Published |
20090111200 | Method for Fabricating Electronic and Photonic Devices on a Semiconductor Substrate - A method for fabricating photonic and electronic devices on a substrate is disclosed. Multiple slabs are initially patterned and etched on a layer of a substrate. An electronic device is fabricated on a first one of the slabs and a photonic device is fabricated on a second one of the slabs, such that the electronic device and the photonic device are formed on the same layer of the substrate. | 04-30-2009 |
20100025364 | Method for Manufacturing Multiple Layers of Waveguides - A method for manufacturing multiple layers of waveguides is disclosed. Initially, a first cladding layer is deposited on a substrate, a first inner cladding layer is then deposited on the first cladding layer, and a first waveguide material is deposited on the first inner cladding layer. The first inner cladding layer and the first waveguide material are then selectively etched to form a first waveguide layer. Next, a second inner cladding layer followed by a second cladding layer are deposited on the first waveguide layer. The second inner cladding layer and the second cladding layer are removed by using a chemical-mechanical polishing process selective to the first waveguide material. A third inner cladding layer followed by a second waveguide material are deposited on the first waveguide material. The third inner cladding layer and the second waveguide material are then selectively etched to form a second waveguide layer. Finally, a fourth inner cladding layer followed by a third cladding layer are deposited on the second waveguide layer. | 02-04-2010 |
20100029033 | Method for Manufacturing Vertical Germanium Detectors - An improved method for manufacturing a vertical germanium detector is disclosed. Initially, a detector window is opened through an oxide layer on a single crystalline substrate. Next, a single crystal germanium layer is grown within the detector window, and an amorphous germanium layer is grown on the oxide layer. The amorphous germanium layer is then polished and removed until only a portion of the amorphous germanium layer is located around the single crystal germanium layer. A tetraethyl orthosilicate (TEOS) layer is deposited on the amorphous germanium layer and the single crystal germanium layer. An implant is subsequently performed on the single crystal germanium layer. After an oxide window has been opened on the TEOS layer, a titanium layer is deposited on the single crystal germanium layer to form a vertical germanium detector. | 02-04-2010 |
20100092682 | Method for Fabricating a Heater Capable of Adjusting Refractive Index of an Optical Waveguide - A method for fabricating a thermal optical heating element capable of adjusting refractive index of an optical waveguide is disclosed. A silicon block is initially formed on a cladding layer on a silicon substrate. The silicon block is located in close proximity to an optical waveguide. A cobalt layer is deposited on the silicon block. The silicon block is then annealed to cause the cobalt layer to react with the silicon block to form a cobalt silicide layer. The silicon block is again annealed to cause the cobalt silicide layer to transform into a cobalt di-silicide layer. | 04-15-2010 |
20100140587 | High-Injection Heterojunction Bipolar Transistor - A method for manufacturing high-injection heterojunction bipolar transistor capable of being used as a photonic device is disclosed. A sub-collector layer is formed on a substrate. A collector layer is then deposited on top of the sub-collector layer. After a base layer has been deposited on top of the collector layer, a quantum well layer is deposited on top of the base layer. An emitter is subsequently formed on top of the quantum well layer. | 06-10-2010 |
20100330727 | Method for Fabricating Butt-Coupled Electro-Absorptive Modulators - A method for fabricating butt-coupled electro-absorptive modulators is disclosed. A butt-coupled electro-absorptive modulator with minimal dislocations in the electro-absorptive material is produced by adding a dielectric spacer for lining the coupling region before epitaxially growing the SiGe or other electro-absorptive material. It has been determined that during the SiGe growth, the current process has exposed single crystal silicon at the bottom of the hole and exposed amorphous silicon on the sides. SiGe growth on the amorphous silicon is expected to have more dislocations than single crystal silicon. There should also be dislocations or fissures where the SiGe growth from the each nucleation source finally join. Thus, a dielectric sidewall can protect an exposed waveguide face from any etching from an aggressive surface preparation prior to epi growth. | 12-30-2010 |
20110039388 | Multi-Thickness Semiconductor With Fully Depleted Devices And Photonic Integration - Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region. | 02-17-2011 |
20120304919 | Method For Growing Germanium Epitaxial Films - A method for growing germanium epitaxial films is disclosed. Initially, a silicon substrate is preconditioned with hydrogen gas. The temperature of the preconditioned silicon substrate is then decreased, and germane gas is flowed over the preconditioned silicon substrate to form an intrinsic germanium seed layer. Next, a mixture of germane and phosphine gases can be flowed over the intrinsic germanium, seed layer to produce an n-doped germanium seed layer. Otherwise, a mixture of diborane and germane gases can be flowed over the intrinsic germanium seed layer to produce a p-doped germanium seed layer. At this point, a hulk germanium layer can be grown on top of the doped germanium seed layer. | 12-06-2012 |
20120321246 | ASYMMETRIC SLOTTED WAVEGUIDE AND METHOD FOR FABRICATING THE SAME - An asymmetric slotted waveguide and method for fabricating the same. The slotted waveguide is constructed in silicon-on-insulator using a Complementary metal-oxide-semiconductor (CMOS) process. One or more wafers can be coated with a photo resist material using a photolithographic process in order to thereby bake the wafers via a post apply bake (PAB) process. An anti-reflective coating (TARC) can be further applied on the wafers and the wafers can be exposed on a scanner for the illumination conditions. After a post exposure bake (PEB), the wafers can be developed in a developer using a puddle develop process. Finally, the printed wafers can be processed using a shrink process to reduce the critical dimension (CD) of the slot and thereby achieve an enhanced asymmetric slotted waveguide that is capable of guiding the optical radiation in a wide range of optical modulation applications using an electro-optic polymer cladding. | 12-20-2012 |
20120322177 | METHOD OF INTEGRATING SLOTTED WAVEGUIDE INTO CMOS PROCESS - A method for integrating a slotted waveguide into a CMOS process is disclosed. A slot can be patterned on a SOI wafer by etching a first pad hard mask deposited over the wafer. The slot is then filled with a plug material by depositing a second pad hard mask over the first pad hard mask. A waveguide in association with one or more electronic and photonic devices can also be patterned on the SOI wafer. The trenches can be filled with an isolation material and then polished. Thereafter, the first and second pad hard masks can be stripped from the wafer. The slot can once again be filled with the plug material and patterned. After forming one or more electronic and photonic devices on the wafer using the standard CMOS process, a via can be opened up down to the nitride plug and the nitride plug can then be removed. | 12-20-2012 |
20140029892 | IN-LINE GERMANIUM AVALANCHE PHOTODETECTOR - A method for manufacturing a photodetector including growing a quantity of germanium within an optical pathway of a waveguide. The detection of a current caused by an interaction between the optical signal and the germanium is used to indicate the presence of an optical signal passing through the waveguide. | 01-30-2014 |
20150016770 | THREE-DIMENSIONAL ELECTRONIC PHOTONIC INTEGRATED CIRCUIT FABRICATION PROCESS - A device and the process for creating a three-dimensional electronic photonic circuit is disclosed. The process includes fabricating a standard high performance integrated circuit on a high resistivity silicon or a silicon-on-insulator substrate up to and including the passivation layer on top of transistors. Separately, a silicon-on-insulator wafer capped by an oxide layer is fabricated, then the two wafers are joined. The resultant device has photonic process elements (e.g. waveguides and photodetectors) fabricated in the top silicon layer. Continued processing interconnects the transistors and photonic elements with contacts and metallization levels to produces an electronic-photonic integrated circuit. | 01-15-2015 |