| Patent application number | Description | Published |
|---|
| 20090132749 | Cache memory system - Systems and methods are disclosed for pre-fetching data into a cache memory system. These systems and methods comprise retrieving a portion of data from a system memory and storing a copy of the retrieved portion of data in a cache memory. These systems and methods further comprise monitoring data that has been placed into pre-fetch memory. | 05-21-2009 |
| 20090132750 | Cache memory system - The present disclosure provides systems and methods for a cache memory and a cache load circuit. The cache load circuit is capable of retrieving a portion of data from the system memory and of storing a copy of the retrieved portion of data in the cache memory. In addition, the systems and methods comprise a monitoring circuit for monitoring accesses to data in the system memory. | 05-21-2009 |
| 20090132768 | Cache memory system - Systems and methods are disclosed that comprise a cache memory for storing a copy of a portion of data stored in a system memory and a cache load circuit capable of retrieving the portion of data from the system memory. The systems and methods further comprise a status memory for identifying whether or not a region of the cache memory contains data that has been accessed from the cache memory by an external device. | 05-21-2009 |
| 20090307433 | Cache memory system - Systems and methods for pre-fetching data are disclosed that use a cache memory for storing a copy of data stored in a system memory and mechanism to initiate a pre-fetch of data from the system memory into the cache memory. The system further comprises an event monitor for monitoring events that is connected to a path on which signals representing an event are transmitted between one or more event generating modules and a processor. In some embodiments, the event monitor initiates a pre-fetch of a portion of data in response to the event monitor detecting an event indicating the availability of the portion of data in the system memory. | 12-10-2009 |
| 20110133825 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND SAMPLED CONTROL SIGNALS - A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A sampling circuit samples the control signals before transport on the interface. The sampling circuit is controlled in dependence on at least one quality of service parameter associated with a respective control signal. | 06-09-2011 |
| 20110133826 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND QUEUE ALLOCATION - A package includes a first die and a second die. The dies are connected to each other through an interface. At least one of the first and second dies includes a plurality of signal sources, wherein each source has at least one quality of service parameter associated therewith, and a plurality of queues having a different priorities. A signal from a respective one of the signal sources is allocated to one of the plurality of queues in dependence on the at least one quality of service parameter associated with the respective signal source. The interface is configured such that signals from said queues are transported from one of said first and second dies to the other of said first and second dies. | 06-09-2011 |
| 20110134705 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND A MULTIPLEXED COMMUNICATIONS INTERFACE - A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A multiplexer is provided to multiplex the control signals and memory transactions onto the interface such that a plurality of connections of said interface are shared by the control signals and the memory transactions. | 06-09-2011 |
| 20110135046 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND A SYNCHRONIZER - A package includes a first die and a second die. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A synchronizer is provided on at least one of said first and second of said dies. The synchronizer is configured to cause any untransmitted control signal values to be transmitted across the interface. | 06-09-2011 |
| 20110138093 | INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND INTERRUPT PROCESSING - A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and providing a packet in response to the interrupt information detection. The packet includes an address to which data in the packet is to be written. The interface is configured to transport the packet between the dies. A data store is provided to which the data is writable. An interrupt event is determined from data received in several packets. | 06-09-2011 |
