Patent application number | Description | Published |
20090083518 | Attaching and virtualizing reconfigurable logic units to a processor - In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and back-end stages, and the execution units are coupled between dispatch ports of the front-end stages and writeback ports of the back-end stages. Further, a reconfigurable logic is coupled between one of the dispatch ports and one of the writeback ports. Other embodiments are described and claimed. | 03-26-2009 |
20100250792 | OPPORTUNISTIC IMPROVEMENT OF MMIO REQUEST HANDLING BASED ON TARGET REPORTING OF SPACE REQUIREMENTS - Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed. | 09-30-2010 |
20110078389 | MANAGING AND IMPLEMENTING METADATA IN CENTRAL PROCESSING UNIT USING REGISTER EXTENSIONS - A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers. | 03-31-2011 |
20110258419 | Attaching And Virtualizing Reconfigurable Logic Units To A Processor - In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and back-end stages, and the execution units are coupled between dispatch ports of the front-end stages and writeback ports of the back-end stages. Further, a reconfigurable logic is coupled between one of the dispatch ports and one of the writeback ports. Other embodiments are described and claimed. | 10-20-2011 |
20130022201 | Encrypted memory - A memory device is operable to perform channel encryption wherein for communication between devices, each includes cryptographic logic and performs cryptographic operations. In an illustrative embodiment, the memory device can comprise memory operable to store data communicated via a communication channel from a processor, and logic operable to perform channel encryption operations on the communication channel that communicates information between the processor and the memory. | 01-24-2013 |
20130024676 | Control flow integrity - In at least some embodiments, a processor in accordance with the present disclosure is operable to enforce control flow integrity. For examiner, a processor may comprise logic operable to execute a control flow integrity instruction specified to verify changes in control flow and respond to verification failure by at least one of a trap or an exception. | 01-24-2013 |
20130024867 | Resource allocation using a library with entitlement - An entitlement vector may be used when selecting a thread for execution in a multi-threading environment in terms of aspects such as priority. An embodiment or embodiments of an information handling apparatus can comprise a library comprising a plurality of functions and components operable to handle a plurality of objects. The information handling apparatus can further comprise an entitlement vector operable to assign entitlement to at least one of a plurality of resources to selected ones of the plurality of functions and components. | 01-24-2013 |
20130024937 | Intrusion detection using taint accumulation - A method operable in a computing device adapted for handling security risk can use taint accumulation to detect intrusion. The method can comprise receiving a plurality of taint indicators indicative of potential security risk from a plurality of distinct sources at distinct times, and accumulating the plurality of taint indicators independently using a corresponding plurality of distinct accumulation functions. Security risk can be assessed according to a risk assessment function that is cumulative of the plurality of taint indicators. | 01-24-2013 |
20130024939 | Conditional security response using taint vector monitoring - An embodiment or embodiments of a computing system can conditionally trap based on a taint vector. A computing system can comprise at least one taint vector operable to list at least one of a plurality of taints indicative of potential security risk originating from at least one of a plurality of resources, and response logic operable to monitor the at least one taint vector and respond to a predetermined taint condition. | 01-24-2013 |
20130031364 | Fine-grained security in federated data sets - A data processing system, a server such as a federated server, a computer system, and like devices, and associated operating methods can be configured to support fine-grained security including resource allocation and resource scheduling. A data processing system can comprise a federated server operable to access data distributed among a plurality of remote data sources upon request from a plurality of client users and applications; and logic executable on the federated server. The logic can be operable to enforce fine-grained security operations on a plurality of federated shared data sets distributed among the plurality of remote data sources. | 01-31-2013 |
20130036314 | Security perimeter - Embodiments of memory devices, computer systems, security apparatus, data handling systems, and the like, and associated methods facilitate security in a system incorporating the concept of a security perimeter which combines cryptographic and physical security. The memory device can comprise a memory operable to store information communicated with a processor, and a logic operable to create at least one cryptographic security perimeter enclosing at least one selected region of the memory and operable to manage information communication between the processor and the at least one selected region of the memory. | 02-07-2013 |
20130036464 | Processor operable to ensure code integrity - A processor can be used to ensure that program code can only be used for a designed purpose and not exploited by malware. Embodiments of an illustrative processor can comprise logic operable to execute a program instruction and to distinguish whether the program instruction is a legitimate branch instruction or a non-legitimate branch instruction. | 02-07-2013 |
20130081039 | Resource allocation using entitlements - A data handling apparatus are adapted to facilitate resource allocation, allocating resources upon which objects execute. A data handling apparatus can comprise resource allocation logic and a scheduler. The resource allocation logic can be operable to dynamically set entitlement value for a plurality of resources comprising physical/logical resources and operational resources. The entitlement value are specified as predetermined rights wherein a process of a plurality of processes is entitled to a predetermined percentage of operational resources. The scheduler can be operable to monitor the entitlement value and schedule the processes based on priority of the entitlement values. | 03-28-2013 |
20130081043 | Resource allocation using entitlement hints - An embodiment of an information handling apparatus can comprise an entitlement vector operable to specify resources used by at least one object of a plurality of a plurality of objects, and logic operable to issue a hint instruction based on the entitlement vector for usage in scheduling the resources. | 03-28-2013 |
20130081134 | Instruction set adapted for security risk monitoring - A processor is adapted to manage security risk by updating and monitoring a taint storage element in response to receipt of taint indicators, and responding to predetermined taint conditions detecting by the monitoring. The processor can be operable to execute instructions of a defined instruction set architecture and comprises an instruction of the instruction set architecture operable to access data from a source and operable to receive a taint indicator indicative of potential security risk associated with the data. The processor can further comprise a taint storage element operable for updating in response to receipt of the taint indicator and logic. The logic can be operable to update the taint storage element, process the taint storage element, determine a security risk condition based on the processing of the taint storage element, and respond to the security risk condition. | 03-28-2013 |
20130111489 | Entitlement vector for managing resource allocation | 05-02-2013 |
20130111491 | Entitlement vector with resource and/or capabilities fields | 05-02-2013 |
20130139262 | Taint injection and tracking - An embodiment or embodiments of an electronic device can comprise an input interface and a hardware component coupled to the input interface. The input interface can be operable to receive a plurality of taint indicators corresponding to at least one of a plurality of taints indicative of potential security risk which are injected from at least one of a plurality of resources. The hardware component can be operable to track the plurality of taints. | 05-30-2013 |
20140223141 | SHARING TLB MAPPINGS BETWEEN CONTEXTS - In some implementations, a processor may include a data structure, such as a translation lookaside buffer, that includes an entry containing first mapping information having a virtual address and a first context associated with a first thread. Control logic may receive a request for second mapping information having the virtual address and a second context associated with a second thread. The control logic may determine whether the second mapping information associated with the second context is equivalent to the first mapping information in the entry of the data structure. If the second mapping information is equivalent to the first mapping information, the control logic may associate the second thread with the first mapping information contained in the entry of the data structure to share the entry between the first thread and the second thread. | 08-07-2014 |