| Patent application number | Description | Published |
|---|
| 20090063780 | DATA PROCESSING SYSTEM AND METHOD FOR MONITORING THE CACHE COHERENCE OF PROCESSING UNITS - The present invention relates to a data processing system with a plurality of processing units (PU), a shared memory (M) for storing data from said processing units (PU) and an interconnect means (IM) for coupling the memory (M) and the plurality of processing units (PU). At least one of the processing units (PU) comprises a cache memory (C). Furthermore, a transition buffer (STB) is provided for buffering at least some of the state transitions of the cache memories (C) of said at least one of said plurality of processing units (PU). A monitoring means (MM) is provided for monitoring the cache coherence of the caches (C) of said plurality of processing units (PU) based on the data of the transition buffer (STB), in order to determine any cache coherence violations. | 03-05-2009 |
| 20100299485 | CIRCUIT AND METHOD WITH CACHE COHERENCE STRESS CONTROL - A circuit contains a shared memory ( | 11-25-2010 |
| 20100328538 | PARALLEL THREE-DIMENSIONAL RECURSIVE SEARCH (3DRS) MEANDERING ALGORITHM - Various exemplary embodiments relate to a method and related motion estimation unit for performing motion estimation on video data comprising a plurality of frames. The method may begin by reading a current frame of the plurality of frames from a memory of a motion estimation unit. The method may then select a motion vector for each respective block of pixels in a current row of the current frame. The step of selecting the motion vector may include, for each respective block, selecting, by the motion estimation unit, a candidate vector for at least one block directly surrounding the respective block based on a determination of whether the directly surrounding block has been processed for the current frame, calculating, for each candidate vector, a difference value, and selecting, as the motion vector, the candidate vector with the lowest difference value. | 12-30-2010 |
| 20110004881 | LOOK-AHEAD TASK MANAGEMENT - A method comprising receiving tasks for execution on at least one processor, and processing at least one task within one processor. To decrease the turn-around time of task processing, a method comprises parallel to processing the at least one task, verifying readiness of at least one next task assuming the currently processed task is finished, preparing a readystructure for the at least one task verified as ready, and starting the at least one task verified as ready using the ready-structure after the currently processed task is finished. | 01-06-2011 |
| 20110082981 | MULTIPROCESSING CIRCUIT WITH CACHE CIRCUITS THAT ALLOW WRITING TO NOT PREVIOUSLY LOADED CACHE LINES - Data is processed using a first and second processing circuit ( | 04-07-2011 |
| 20110093661 | MULTIPROCESSOR SYSTEM WITH MIXED SOFTWARE HARDWARE CONTROLLED CACHE MANAGEMENT - A multiprocessor system has a background memory and a plurality of processing elements ( | 04-21-2011 |
| 20110099337 | PROCESSING CIRCUIT WITH CACHE CIRCUIT AND DETECTION OF RUNS OF UPDATED ADDRESSES IN CACHE LINES - A circuit that comprises a processor core ( | 04-28-2011 |
| 20110107345 | MULTIPROCESSOR CIRCUIT USING RUN-TIME TASK SCHEDULING - Tasks are executed in a multiprocessing system with a master processor core ( | 05-05-2011 |
