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Andreev, US
Alexander E. Andreev, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090094571 | Method and system for outputting a sequence of commands and data described by a flowchart - The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x | 04-09-2009 |
| 20090133003 | COMMAND LANGUAGE FOR MEMORY TESTING - A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing. | 05-21-2009 |
| 20100031126 | System and method for using the universal multipole for the implementation of a configurable binary bose-chaudhuri-hocquenghem (BCH) encoder with variable number of errors - The present invention is a configurable binary BCH encoder having a variable number of errors. The encoder may implement a universal multipole block which may be configured for receiving an error number input, which may include a maximum error number limit for the encoder, and for calculating a plurality of error coefficients based on the error number input. The encoder may be further configured for receiving a plurality of information bits of an information word. The encoder may be further configured for transmitting/outputting a first (ex.—unmodified) subset of the information bits as an encoder output. The encoder may be further configured for calculating a plurality of parity bits based on a second subset of the information bits and the error coefficients. The encoder may be further configured for transmitting/outputting the calculated parity bits as part of the encoder output. | 02-04-2010 |
Alexander E. Andreev US
| Patent application number | Description | Published |
|---|---|---|
| 20120079345 | SYSTEM AND METHOD FOR ASSIGNING CODE BLOCKS TO CONSTITUENT DECODER UNITS IN A TURBO DECODING SYSTEM HAVING PARALLEL DECODING UNITS - A system for, and method of, assigning code blocks to constituent decoding units in a turbo decoding system having parallel decoding units. In one embodiment, the method includes: (1) representing the turbo decoding system as a resource diagram rectangle, (2) representing the code blocks as code block rectangles, (3) mapping the code block rectangles into the resource diagram rectangle and (4) assigning the code blocks to the constituent decoding units based on the mapping. | 03-29-2012 |
Alexandre E. Andreev, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090316507 | Generation Of Test Sequences During Memory Built-In Self Testing Of Multiple Memories - The present invention concerns an apparatus including a modular memory and an address locator circuit. The modular memory may be configured to generate a current address signal, a first data output signal and a second data output signal in response to a first port address signal, a second port address signal, an initial state parameter, a target state parameter, a first port enable signal, a second port enable signal, a write enable signal, a data input signal, a first location signal and a second location signal. The address locator circuit may be configured to generate the first location signal and the second location signal in response to the first port address signal, the second port address signal and the current address signal. | 12-24-2009 |
Anatoli S. Andreev, Chassell, MI US
| Patent application number | Description | Published |
|---|---|---|
| 20100223505 | SOFTWARE TABLE WALK DURING TEST VERIFICATION OF A SIMULATED DENSELY THREADED NETWORK ON A CHIP - A computer-implemented method, system and computer program product are presented for managing an Effective-to-Real Address Table (ERAT) and a Translation Lookaside Buffer (TLB) during test verification in a simulated densely threaded Network On a Chip (NOC). The ERAT and TLB are stripped out of the computer simulation before executing a test program. When the test program experiences an inevitable ERAT-miss and/or TLB-miss, an interrupt handler walks a page table until the requisite page for re-populating the ERAT and TLB is located. | 09-02-2010 |
Boris Andreev, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110193589 | On-Chip Sensor For Measuring Dynamic Power Supply Noise Of The Semiconductor Chip - An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured. | 08-11-2011 |
Boris Dimitrov Andreev, San Diego, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090039867 | Circuit Device and Method of Measuring Clock Jitter - In an embodiment, a method is disclosed that includes receiving a clock signal at a delay chain of a circuit device and determining a value of the clock signal at a selected point within the delay chain. The method also includes adjusting the selected point when the value does not indicate detection of an edge of the clock signal. | 02-12-2009 |
| 20110111705 | System and Method of Silicon Switched Power Delivery Using a Package - In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first package-substrate connection, a second package-substrate connection, and metallization coupling the first package-substrate connection to the second package-substrate connection. The substrate is coupled to the package via the first package-substrate connection and the second package-substrate connection. The substrate includes a plurality of power domains and a power control unit. The second package-substrate connection of the package is coupled to a particular power domain of the plurality of power domains. The power control unit includes logic and a switch, where the switch includes a first terminal coupled to a voltage supply terminal, a control terminal coupled to the logic, and a second terminal coupled to the first package-substrate connection of the package. The logic selectively activates the switch to distribute power to the particular power domain via the metallization of the package. | 05-12-2011 |
Cristian Andreev, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100066321 | CIRCUITS AND METHODS FOR CURRENT SENSING - A current sensing circuit includes a first resistor, a second resistor and a sense amplifier. The first resistor converts a current flowing through the first resistor to a voltage drop between positive and negative sides of the first resistor. The second resistor is coupled to the negative side of the first resistor. The sense amplifier is coupled to the positive side of the first resistor via a first pin of the sense amplifier, and coupled to the negative side of the first resistor through the second resistor via a second pin of the sense amplifier. The sense amplifier employs a negative feedback to generate a sensing current proportional to the current flowing through the first resistor. | 03-18-2010 |
Dmitrii Andreev, Port Chester, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090210275 | COST MANAGEMENT OF SOFTWARE APPLICATION PORTFOLIO - An apparatus for managing a cost of ownership of a portfolio of N software applications (N≧2). A regression function is identified for each application. Each regression function expresses an approximate cost of ownership of the applications in terms of parameters and coefficients. J applications A | 08-20-2009 |
| 20100122185 | SYSTEM FOR MESSAGING AND COLLABORATING IN AN INTRANET ENVIRONMENT - A messaging system and associated computer program product. The messaging system includes a plurality of browsers connected through a common server. The server includes a message engine for receiving from a first user browser a request to enter chat mode with a second user browser; then receiving asynchronously from the second user browser a request to download any content from the common server or any other intranet or Internet server; and responding to the request from the second user browser with content modified to instantiate a chat session between the first and second user browsers. | 05-13-2010 |
Dmitry Andreev, Syracuse, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090019363 | METHOD FOR GENERATING AND PRIORITIZING MULTIPLE SEARCH RESULTS - A method for generating and prioritizing multiple search results is disclosed. A database stores search results in an information storage and retrieval system. A search program executes on a computer system coupled to the database. The search program receives a search request from a user input. The search program parses the search request into at least one search term. The search program performs a loop comprising steps associating a priority adjustment value with each search term, generating a search result, calculating a priority adjustment sum of the generated search result, inserting the at least one search term, the generated search result, and the calculated priority adjustment sum in the search result list, and modifying the at least one search term and the priority adjustment value associated with each search term to perform a next iteration of the loop. | 01-15-2009 |
Dmitry Andreev, Larchmont, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090126000 | SINGLE SIGN-ON METHOD FOR WEB-BASED APPLICATIONS - A method for single-sign on of a user on a client machine to one or more target applications on target application servers in a computer information-processing network, including: accessing an access server from the client machine; entering user-specific access server logon credentials for logon and access to the access server; selecting a target application; presenting to the target application by the access server, previously stored user-specific target application logon credentials for logon and access to the target application in a form and according to a protocol recognizable by the target application thereby logging into the target application on behalf of the user and establishing a target application session; sending from the access server to the client machine, information for establishing a connection from the client machine to the target application; and establishing a target application session, bypassing the access server, between the client machine and the target application. | 05-14-2009 |
Dmitry Andreev, Port Chester, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090204693 | OPTIMIZATION OF ASPECTS OF INFORMATION TECHNOLOGY STRUCTURES - A computer system and computer program product for optimizing an aspect of an Information Technology (IT) structure of an IT system. The aspect of the IT structure is optimized with respect to at least one control parameter. The IT structure includes a plurality of elements. Each element independently is a hardware element, a software element, or a combination of a hardware element and a software element. Each control parameter has a value that is specific to each element of the IT structure. | 08-13-2009 |
| 20090287808 | AUTOMATED DISPLAY OF AN INFORMATION TECHNOLOGY SYSTEM CONFIGURATION - An Information Technology (IT) system display method and computer program product. A description is provided of a configuration of devices, network segments, and vertical connectors relating to an IT structure. The devices are initially distributed to form a distribution of the devices in a matrix representing a display screen. A defined goal value of the configuration is a function of a length and weight of each network segment, a length and weight of each vertical connector, and a penalty for each crossing of a device by a network segment. An overlay pattern of the network segments and the vertical connectors overlayed on the matrix is displayed in accordance with the description and the final distribution of the devices in the matrix. The goal value for the final distribution is lower than for the initial distribution. The final distribution is displayed on the display screen together with the overlay pattern. | 11-19-2009 |
Oleg A. Andreev, West Kingston, RI US
| Patent application number | Description | Published |
|---|---|---|
| 20080233107 | SELECTIVE DELIVERY OF MOLECULES INTO CELLS OR MARKING OF CELLS IN DISEASED TISSUE REGIONS USING ENVIRONMENTALLY SENSITIVE TRANSMEMBRANE PEPTIDE - A polypeptide with a predominantly hydrophobic sequence long enough to span a membrane lipid bilayer as a transmembrane helix (TM) and comprising one or more dissociable groups inserts across a membrane spontaneously in a pH-dependant fashion placing one terminus inside cell. The polypeptide conjugated with various functional moieties delivers and accumulates them at cell membrane with low extracellular pH. The functional moiety conjugated with polypeptide terminus placed inside cell are translocated through the cell membrane in cytosol. The peptide and its variants or non-peptide analogs can be used to deliver therapeutic, prophylactic, diagnostic, imaging, gene regulation, cell regulation, or immunologic agents to or inside of cells in vitro or in vivo in tissue at low extracellular pH. The claimed method provides a new approach for diagnostic and treatment diseases with naturally occurred (or artificially created) low pH extracellular environment such as tumors, infarction, stroke, atherosclerosis, inflammation, infection, or trauma. The method allows to translocate cell impermeable molecules (peptides, toxins, drugs, inhibitors, nucleic acids, peptide nucleic acids, imaging probes) into cells at low pH. The method allows to attach to the cell surface a variety of functional moieties and particles including peptides, polysaccharides, virus, antigens, liposomes and nanoparticles made of any materials. | 09-25-2008 |
Oleg A. Andreev, South Kingstown, RI US
| Patent application number | Description | Published |
|---|---|---|
| 20120039990 | Liposome Compositions and Methods of Use Thereof - The present application relates to compositions comprising and methods of using a liposome comprising a pHLIP polypeptide, wherein a lipid bilayer of the liposome is substantially free of the pHLIP polypeptide. | 02-16-2012 |