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Anda
Robert Anda, Miami, FL US
| Patent application number | Description | Published |
|---|---|---|
| 20090052810 | COMPARTMENTED RESEALABLE PLASTIC BAG - A compartmented resealable plastic bag comprising a plastic bag having a top, a bottom and two lateral sides, an inner plastic bag liner attached to the plastic bag, the plastic bag defines a resealable closure adjacent to the top of the plastic bag, the inner plastic bag liner and the plastic bag are heat sealed together so that channels are defined between the plastic bag and the inner plastic bag liner, the channels are positioned so that each channel is flush with another channel when the bag lies flat and each channel runs parallel to the lateral sides of the plastic bag, and at least a pair of rods, the rods insert within the channels that lie flush to each other. The rods possess magnetic qualities. | 02-26-2009 |
Roger Anda, Kleppe NO
| Patent application number | Description | Published |
|---|---|---|
| 20080197646 | Lifting Anchor - A lifting anchor ( | 08-21-2008 |
Yoshiharu Anda, Osaka JP
| Patent application number | Description | Published |
|---|---|---|
| 20090230482 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device in which an E-FET and a D-FET are integrated on the same substrate, wherein an epitaxial layer includes, in the following order from the semiconductor substrate: a first threshold adjustment layer that adjusts a threshold voltage of a gate of the E-FET and a threshold voltage of a gate of the D-FET; a first etching-stopper layer that stops etching performed from an uppermost layer to a layer abutting on the first etching-stopper layer; a second threshold adjustment layer that adjusts the threshold voltage of the gate of the D-FET; and a second etching-stopper layer that stops the etching performed from the uppermost layer to a layer abutting on the second etching-stopper layer, and at least one of the first etching-stopper layer and the second threshold adjustment layer includes an n-type doped region. | 09-17-2009 |
| 20090309134 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A multilayer structure including a first electron supply layer and a second electron supply layer is used for an electron supply layer. A multilayer structure including an SiN film and an SiO | 12-17-2009 |
Yoshiharu Anda, Toyama JP
| Patent application number | Description | Published |
|---|---|---|
| 20080251837 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET on the same semiconductor substrate includes: a first threshold adjustment layer for adjusting threshold of the E-FET; a first etching stopper layer formed on the first threshold adjustment layer; the second threshold adjustment layer formed on the first etching stopper layer for adjusting threshold of the D-FET; a second etching stopper layer formed on the second threshold adjustment layer; a first gate electrode penetrating through the first etching stopper layer, the second threshold adjustment layer, and the second etching stopper layer, which is in contact with the first threshold adjustment layer; and the second gate electrode penetrating through the second etching stopper layer, which is in contact with the second threshold adjustment layer. | 10-16-2008 |