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Ananthan, US

Subramaniam Ananthan, Birmingham, AL US

Patent application numberDescriptionPublished
20080312329Nonpeptide Inhibitors of Matrix Metalloproteinases - Disclosed are selective inhibitors of matrix metalloproteinases represented by the following formula (I).12-18-2008
20090239892PYRIDOMORPHINANS, PYRIDAZINOMORPHINANS AND USE THEREOF - Compounds represented by the formula:09-24-2009
20100120745ANTI-ANGIOGENIC AGENTS AND METHODS OF USE - The present disclosure relates generally to treating or preventing diseases associated with angiogenesis by administering to a patient certain compounds found to inhibit or substantially reduce angiogenesis. Compounds employed according to the present disclosure exhibit good anti-angiogenic activity as well as demonstrate a prophylactic effect for preventing and substantially reducing angiogenesis. Examples of such compounds include Ritanserin, Amiodarone, Terfenadine, Perphenazine, Bithionol, and Clomipramine.05-13-2010
20100204338ANTI-ANGIOGENIC AGENTS AND METHODS OF USE - The present disclosure relates generally to treating or preventing diseases associated with angiogenesis by administering to a patient certain compounds found to inhibit or substantially reduce angiogenesis. Compounds employed according to the present disclosure exhibit good anti-angiogenic activity as well as demonstrate a prophylactic effect for preventing and substantially reducing angiogenesis. Examples of such compounds include Ritanserin, Amiodarone, Terfenadinc, Perphenazine, Bithionol, and Clomipramine.08-12-2010
20110060000ACRIDINE ANALOGS IN THE TREATMENT OF GLIOMAS - Disclosed are methods and compositions for treating gliomas that involve quinacrine and other acridine analogs. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present invention.03-10-2011

Patent applications by Subramaniam Ananthan, Birmingham, AL US

Venkat Ananthan, Boise, ID US

Patent application numberDescriptionPublished
20080277738MEMORY CELLS, MEMORY BANKS, MEMORY ARRAYS, AND ELECTRONIC SYSTEMS - Some embodiments include memory cells containing vertical floating bodies, and containing gates which entirely laterally surround the floating bodies. Some embodiments include memory banks which contain multiple memory cells extending from a conductively-doped diffusion region. Some embodiments include memory arrays in which electrically insulative partitions extend through a conductively-doped diffusion region to divide the diffusion region into a plurality of lines, and in which multiple memory cells extend vertically upward from each of such lines. Some embodiments include electronic systems containing processors in data communication with memory, and in which the memory includes an array of zero capacitor one transistor memory cells. Some embodiments include methods of forming vertically-extending memory cells. Some embodiments include methods of forming of banks of memory cells in which all of the memory cells extend to a conductively-doped region. Some embodiments include methods of forming memory arrays.11-13-2008

Venkatesan Ananthan, Boise, ID US

Patent application numberDescriptionPublished
20090026522SEMICONDUCTOR DEVICE COMPRISING TRANSISTOR STRUCTURES AND METHODS FOR FORMING SAME - A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.01-29-2009
20090206418Semiconductor Constructions - The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.08-20-2009
20110006365Semiconductor Device Comprising Transistor Structures and Methods for Forming Same - A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.01-13-2011
20110042754Gate Stacks and Semiconductor Constructions - The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.02-24-2011

Patent applications by Venkatesan Ananthan, Boise, ID US

Venkatesan Ananthan, Santa Clara, CA US

Patent application numberDescriptionPublished
20090236657IMPACT IONIZATION DEVICES AND METHODS OF MAKING THE SAME - Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of forming such devices are disclosed. The devices require lower threshold voltage than conventional MOSET devices while maintaining a footprint equal to or less than conventional MOSFET devices.09-24-2009