| Patent application number | Description | Published |
|---|
| 20090146154 | Transistor with A-Face Conductive Channel and Trench Protecting Well Region - A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner. | 06-11-2009 |
| 20090189228 | SEMICONDUCTOR TRANSISTOR WITH P TYPE RE-GROWN CHANNEL LAYER - The invention is a device for controlling conduction across a semiconductor body with a P type channel layer between active semiconductor regions of the device and the controlling gate contact. The device, often a MOSFET or an IGBT, includes at least one source, well, and drift region. The P type channel layer may be divided into sections, or divided regions, that have been doped to exhibit N type conductivity. By dividing the channel layer into regions of different conductivity, the channel layer allows better control over the threshold voltage that regulates current through the device. Accordingly, one of the divided regions in the channel layer is a threshold voltage regulating region. The threshold-voltage regulating region maintains its original P type conductivity and is available in the transistor for a gate voltage to invert a conductive zone therein. The conductive zone becomes the voltage regulated conductive channel within the device. | 07-30-2009 |
| 20090233418 | Methods of Processing Semiconductor Wafers Having Silicon Carbide Power Devices Thereon - Methods of forming a silicon carbide semiconductor device are disclosed. The methods include forming a semiconductor device at a first surface of a silicon carbide substrate having a first thickness, and mounting a carrier substrate to the first surface of the silicon carbide substrate. The carrier substrate provides mechanical support to the silicon carbide substrate. The methods further include thinning the silicon carbide substrate to a thickness less the first thickness, forming a metal layer on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate, and locally annealing the metal layer to form an ohmic contact on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate. The silicon carbide substrate is singulated to provide a singulated semiconductor device. | 09-17-2009 |
| 20090315036 | SEMICONDUCTOR DEVICES INCLUDING SCHOTTKY DIODES HAVING DOPED REGIONS ARRANGED AS ISLANDS AND METHODS OF FABRICATING SAME - A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type and a surface in which an active region of the semiconductor device is defined. A plurality of spaced apart first doped regions are arranged within the active region. The plurality of first doped regions have a second conductivity type that is opposite the first conductivity type, have a first dopant concentration, and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of first doped regions are arranged as islands in the semiconductor layer. A second doped region in the semiconductor layer has the second conductivity type and has a second dopant concentration that is greater than the first dopant concentration. | 12-24-2009 |
| 20100090271 | Power Switching Semiconductor Devices Including Rectifying Junction-Shunts - A semiconductor device includes a drift layer having a first conductivity type and a body region adjacent the drift layer. The body region has a second conductivity type opposite the first conductivity type and forms a p-n junction with the drift layer. The device further includes a contactor region in the body region and having the first conductivity type, and a shunt channel region extending through the body region from the contactor region to the drift layer. The shunt channel region has the first conductivity type. The device further includes a first terminal in electrical contact with the body region and the contactor region, and a second terminal in electrical contact with the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse biase the p-n junction between the drift region and the body region. | 04-15-2010 |
| 20100133550 | STABLE POWER DEVICES ON LOW-ANGLE OFF-CUT SILICON CARBIDE CRYSTALS - A silicon carbide-based power device includes a silicon carbide drift layer having a planar surface that forms an off-axis angle with a < | 06-03-2010 |
| 20110250737 | TRANSISTOR WITH A-FACE CONDUCTIVE CHANNEL AND TRENCH PROTECTING WELL REGION - A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner. | 10-13-2011 |
| 20120018737 | ELECTRONIC DEVICE STRUCTURE INCLUDING A BUFFER LAYER ON A BASE LAYER - Electronic device structures that compensate for non-uniform etching on a semiconductor wafer and methods of fabricating the same are disclosed. In one embodiment, the electronic device includes a number of layers including a semiconductor base layer of a first doping type formed of a desired semiconductor material, a semiconductor buffer layer on the base layer that is also formed of the desired semiconductor material, and one or more contact layers of a second doping type on the buffer layer. The one or more contact layers are etched to form a second contact region of the electronic device. The buffer layer reduces damage to the semiconductor base layer during fabrication of the electronic device. Preferably, a thickness of the semiconductor buffer layer is selected to compensate for over-etching due to non-uniform etching on a semiconductor wafer on which the electronic device is fabricated. | 01-26-2012 |
| 20120018738 | ELECTRONIC DEVICE STRUCTURE WITH A SEMICONDUCTOR LEDGE LAYER FOR SURFACE PASSIVATION - Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer. | 01-26-2012 |
