| Patent application number | Description | Published |
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| 20090020433 | Electrochemical Fabrication Methods for Producing Multilayer Structures Including the use of Diamond Machining in the Planarization of Deposits of Material - Electrochemical fabrication methods for forming single and multilayer mesoscale and microscale structures are disclosed which include the use of diamond machining (e.g. fly cutting or turning) to planarize layers. Some embodiments focus on systems of sacrificial and structural materials which are useful in Electrochemical fabrication and which can be diamond machined with minimal tool wear (e.g. Ni—P and Cu, Au and Cu, Cu and Sn, Au and Cu, Au and Sn, and Au and Sn—Pb), where the first material or materials are the structural materials and the second is the sacrificial material). Some embodiments focus on methods for reducing tool wear when using diamond machining to planarize structures being electrochemically fabricated using difficult-to-machine materials (e.g. by depositing difficult to machine material selectively and potentially with little excess plating thickness, and/or pre-machining depositions to within a small increment of desired surface level (e.g. using lapping or a rough cutting operation) and then using diamond fly cutting to complete he process, and/or forming structures or portions of structures from thin walled regions of hard-to-machine material as opposed to wide solid regions of structural material. | 01-22-2009 |
| 20090065142 | Method of Electrochemically Fabricating Multilayer Structures Having Improved Interlayer Adhesion - Multi-layer microscale or mesoscale structures are fabricated with adhered layers (e.g. layers that are bonded together upon deposition of successive layers to previous layers) and are then subjected to a heat treatment operation that enhances the interlayer adhesion significantly. The heat treatment operation is believed to result in diffusion of material across the layer boundaries and associated enhancement in adhesion (i.e. diffusion bonding). Interlayer adhesion and maybe intra-layer cohesion may be enhanced by heat treating in the presence of a reducing atmosphere that may help remove weaker oxides from surfaces or even from internal portions of layers. | 03-12-2009 |
| 20090320990 | Electrochemical Fabrication Process for Forming Multilayer Multimaterial Microprobe Structures - Some embodiments of the invention are directed to the electrochemical fabrication of microprobes which are formed from a core material and a material that partially coats the surface of the probe. Other embodiments are directed to the electrochemical fabrication of microprobes which are formed from a core material and a material that completely coats the surface of each layer from which the probe is formed including interlayer regions. These first two groups of embodiments incorporate both the core material and the coating material during the formation of each layer. Still other embodiments are directed to the electrochemical fabrication of microprobe arrays that are partially encapsulated by a dielectric material during a post layer formation coating process. In even further embodiments, the electrochemical fabrication of microprobes from two or more materials may occur by incorporating a coating material around each layer of the structure without locating the coating material in inter-layer regions. | 12-31-2009 |
| 20100051466 | Method of Forming Electrically Isolated Structures Using Thin Dielectric Coatings - Electrochemical fabrication processes and apparatus for producing multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers including operations for providing coatings of dielectric material that isolate at least portions of a first conductive material from (1) other portions of the first conductive material, (2) a second conductive material, or (3) another dielectric material, and wherein the thickness of the dielectric coatings are thin compared to the thicknesses of the layers used in forming the structures. In some preferred embodiments, portions of each individual layer are encapsulated by dielectric material while in other embodiments only boundaries between distinct regions of materials are isolated from one another by dielectric barriers. | 03-04-2010 |
| 20100068837 | Structures and Methods for Wafer Packages, and Probes - This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices. In some embodiments, such structures are shown to be useful for simultaneously testing multiple devices on a semiconductor wafer, or for assembling multiple substrates on to a wafer, to accomplish both testing and packaging of the dies on the wafer. In yet another embodiment of the invention, single or multilevel ceramic interconnect structures with thick film metal conductors, are fabricated right on the product wafer to facilitate economical testing and packaging of the dies on the wafer. | 03-18-2010 |
| 20100090339 | Structures and Methods for Wafer Packages, and Probes - This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices. In some embodiments, such structures are shown to be useful for simultaneously testing multiple devices on a semiconductor wafer, or for assembling multiple substrates on to a wafer, to accomplish both testing and packaging of the dies on the wafer. In yet another embodiment of the invention, single or multilevel ceramic interconnect structures with thick film metal conductors, are fabricated right on the product wafer to facilitate economical testing and packaging of the dies on the wafer. | 04-15-2010 |
| 20100119917 | Seal compositions, methods, and structures for planar solid oxide fuel cells - A seal composition includes a first alkaline earth metal oxide, a second alkaline earth metal oxide which is different from the first alkaline earth metal oxide, aluminum oxide, and silica in an amount such that molar percent of silica in the composition is at least five molar percent greater than two times a combined molar percent of the first alkaline earth metal oxide and the second alkaline earth metal oxide. The composition is substantially free of boron oxide and phosphorus oxide. The seal composition forms a glass ceramic seal which includes silica containing glass cores located in a crystalline matrix comprising barium aluminosilicate, and calcium aluminosilicate crystals located in the glass cores. | 05-13-2010 |
| 20100155253 | Microprobe Tips and Methods for Making - Embodiments of the present invention are directed to the formation of microprobe tips elements having a variety of configurations. In some embodiments tips are formed from the same building material as the probes themselves, while in other embodiments the tips may be formed from a different material and/or may include a coating material. In some embodiments, the tips are formed before the main portions of the probes and the tips are formed in proximity to or in contact with a temporary substrate. Probe tip patterning may occur in a variety of different ways, including, for example, via molding in patterned holes that have been isotropically or anisotropically etched silicon, via molding in voids formed in exposed photoresist, via molding in voids in a sacrificial material that have formed as a result of the sacrificial material mushrooming over carefully sized and located regions of dielectric material, via isotropic etching of the tip material around carefully sized and placed etching shields, via hot pressing, and the like. | 06-24-2010 |
| 20100159344 | Fuel cell seals - A fuel cell stack includes a plurality of fuel cells, a plurality of interconnects, and a plurality of seal members, wherein the plurality of seal members comprises one or more first seal members and one or more additional seal members, where the one or more first seal members form a protective barrier between the reducing environment contained with the fuel cell stack and the remaining seal members. | 06-24-2010 |
| 20100239937 | Crack free SOFC electrolyte - A solid oxide fuel cell (SOFC) stack includes a plurality of SOFCs, and a plurality of interconnects, each interconnect containing a conductive perovskite layer on an air side of the interconnect. The stack in internally manifolded for fuel and the conductive perovskite layer on each interconnect is not exposed in the fuel inlet riser. The SOFC electrolyte has a smaller roughness in regions adjacent to the fuel inlet and fuel outlet openings in the electrolyte than under the cathode or anode electrodes. | 09-23-2010 |
| 20110132767 | Multi-Layer, Multi-Material Fabrication Methods for Producing Micro-Scale and Millimeter-Scale Devices with Enhanced Electrical and/or Mechanical Properties - Some embodiments of the invention are directed to electrochemical fabrication methods for forming structures or devices (e.g. microprobes for use in die level testing of semiconductor devices) from a core material and a shell or coating material that partially coats the surface of the structure. Other embodiments are directed to electrochemical fabrication methods for producing structures or devices (e.g. microprobes) from a core material and a shell or coating material that completely coats the surface of each layer from which the probe is formed including interlayer regions. Additional embodiments of the invention are directed to electrochemical fabrication methods for forming structures or devices (e.g. microprobes) from a core material and a shell or coating material wherein the coating material is located around each layer of the structure without locating the coating material in inter-layer regions. Each of these groups of embodiments incorporate both the core material and the coating material during the formation of each layer and each layer is also formed with a sacrificial material that is removed after formation of all layers of the structure. In some embodiments the core material may be a genuine structural material while in others it may be only a functional structural material (i.e. a material that would be removed with sacrificial material if it were accessible by an etchant during removal of sacrificial material. | 06-09-2011 |
| 20110155580 | Method of Electrochemically Fabricating Multilayer Structures Having Improved Interlayer Adhesion - Multi-layer microscale or mesoscale structures are fabricated with adhered layers (e.g. layers that are bonded together upon deposition of successive layers to previous layers) and are then subjected to a heat treatment operation that enhances the interlayer adhesion significantly. The heat treatment operation is believed to result in diffusion of material across the layer boundaries and associated enhancement in adhesion (i.e. diffusion bonding). Interlayer adhesion and maybe intra-layer cohesion may be enhanced by heat treating in the presence of a reducing atmosphere that may help remove weaker oxides from surfaces or even from internal portions of layers. | 06-30-2011 |
