Patent application number | Description | Published |
20090177451 | APPARATUS AND METHOD FOR ACCELERATING SIMULATIONS AND DESIGNING INTEGRATED CIRCUITS AND OTHER SYSTEMS - A method of accelerating a Monte Carlo (MC) simulation for a system including a first component having a first input parameter and a second component having a second input parameter. The simulation model provided includes a first component model including a first model parameter corresponding to the first input parameter and a second component model having a second model parameter corresponding to the second input parameter. A first acceleration factor for the first component and a second acceleration factor for the second component are calculated based on at least the respective number of instances. A first scaled distribution is computed from the first distribution and a second scaled distribution is computed from the second distribution based on the respective acceleration factors. The MC simulation for the system is run, wherein values for the first model parameter value and second model parameter value are obtained based on the respective scaled distributions. | 07-09-2009 |
20100038684 | Transistor layout for manufacturing process control - A symmetrical circuit is disclosed ( | 02-18-2010 |
20100296332 | SRAM Cell for Single Sided Write - A first integrated circuit containing a single sided write SRAM cell array, each SRAM cell having a bit passgate and an auxiliary bit-bar driver transistor. A process of operating the first integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are floated. A second integrated circuit containing an SRAM cell array, in which each SRAM cell includes a bit-side write passgate, a bit-bar-side read passgate and a bit-bar auxiliary driver transistor. A process of operating the second integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are biased to a low bias voltage. | 11-25-2010 |
20100296334 | 6T SRAM Cell with Single Sided Write - An SRAM cell containing an auxiliary driver transistor is configured for a single sided write operation. The auxiliary driver transistor may be added to a 5-transistor single-sided-write SRAM cell or to a 7-transistor single-sided-write SRAM cell. The SRAM cell may also include a read buffer. During read operations, the auxiliary drivers are biased. During write operations, the auxiliary drivers in half-addressed SRAM cells are biased and the auxiliary drivers in the addressed SRAM cells may be floated or biased. | 11-25-2010 |
20100297815 | Transistor Layout for Manufacturing Process Control - A symmetrical circuit is disclosed (FIG. | 11-25-2010 |
20110261609 | Retain-Till-Accessed Power Saving Mode in High-Performance Static Memories - Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells of the 8-T or 10-T type, with separate read and write data paths. Bias devices are included within each memory array block, for example associated with individual columns, and connected between a reference voltage node for cross-coupled inverters in each memory cell in the associated column or columns, and a ground node. In a normal operating mode, a switch transistor connected in parallel with the bias devices is turned on, so that the ground voltage biases the cross-coupled inverters in each cell. In the RTA mode, the switch transistors are turned off, allowing the bias devices to raise the reference bias to the cross-coupled inverters, reducing power consumed by the cells in that mode. | 10-27-2011 |
20110261629 | Reduced Power Consumption in Retain-Till-Accessed Static Memories - Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells formed of array transistors; functional and other circuitry outside of the array are formed of core transistors, constructed differently from the array transistors. Bias devices are included within each memory array block, the bias devices constructed as one or more array transistors. The bias devices for a memory array block may be connected in parallel with one another. In the RTA mode, the bias devices drop the power supply voltage differential across each of the SRAM cells. In a normal operating mode, a core transistor serves as a switch, shorting out the bias devices so that the full power supply differential appears across the SRAM cells. | 10-27-2011 |
20120106225 | Array-Based Integrated Circuit with Reduced Proximity Effects - An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array. | 05-03-2012 |
20120119824 | BIAS VOLTAGE SOURCE - An integrated circuit that includes a data storage cell. The data storage cell has a PMOS transistor in an n-well. In addition, the data storage cell has a PMOS diode connecting a voltage source to a bias node of the n-well. Alternatively, an integrated circuit that includes a data storage cell. The alternative data storage cell has an NMOS transistor in an isolated p-well. In addition, the alternative data storage cell has an NMOS diode connecting a voltage source to a bias node of the isolated p-well. | 05-17-2012 |
20120127783 | SRAM Cell for Single Sided Write - A first integrated circuit containing a single sided write SRAM cell array, each SRAM cell having a bit passgate and an auxiliary bit-bar driver transistor. A process of operating the first integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are floated. A second integrated circuit containing an SRAM cell array, in which each SRAM cell includes a bit-side write passgate, a bit-bar-side read passgate and a bit-bar auxiliary driver transistor. A process of operating the second integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are biased to a low bias voltage. | 05-24-2012 |
20120195108 | SRAM CELL HAVING A P-WELL BIAS - A process of performing an SRAM single sided write operation including applying a positive bias increment to an isolated p-well containing a passgate in an addressed SRAM cell. A process of performing an SRAM single sided read operation including applying a negative bias increment to an isolated p-well containing a driver in an addressed SRAM cell. A process of performing an SRAM double sided write operation including applying a positive bias increment to an isolated p-well containing a passgate connected to a low data line in an addressed SRAM cell. A process of performing an SRAM double sided read operation including applying a negative bias increment to an isolated p-well containing a bit driver and applying a negative bias increment to an isolated p-well containing a bit-bar driver in an addressed SRAM cell. | 08-02-2012 |
20120201072 | SRAM CELL HAVING AN N-WELL BIAS - An integrated circuit containing SRAM cells. Each SRAM cell has a PMOS driver transistor, a PMOS passgate transistor, and at least two separate n-wells. The integrated circuit also has an n-well bias control circuit that is configured to independently bias the n-wells of an addressed SRAM cell. Moreover, a process of operating an integrated circuit that contains SRAM cells. The process includes writing a low data bit value, writing a high data bit value, and reading a data bit value of an addressed SRAM cell. | 08-09-2012 |
20120324314 | Low Power Retention Random Access Memory with Error Correction on Wake-Up - Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode. | 12-20-2012 |
20130044536 | ARRAY-BASED INTEGRATED CIRCUIT WITH REDUCED PROXIMITY EFFECTS - An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array. | 02-21-2013 |
20130058177 | Method of Screening Static Random Access Memory Cells for Positive Bias Temperature Instability - A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, static noise margin and writeability (V | 03-07-2013 |
20130148416 | SRAM CELL HAVING AN N-WELL BIAS - An integrated circuit containing SRAM cells. Each SRAM cell has a PMOS driver transistor, a PMOS passgate transistor, and at least two separate n-wells. The integrated circuit also has an n-well bias control circuit that is configured to independently bias the n-wells of an addressed SRAM cell. Moreover, a process of operating an integrated circuit that contains SRAM cells. The process includes writing a low data bit value, writing a high data bit value, and reading a data bit value of an addressed SRAM cell. | 06-13-2013 |
20130182490 | Static Random Access Memory Cell with Single-Sided Buffer and Asymmetric Construction - Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature. | 07-18-2013 |
20140327082 | SRAM WELL-TIE WITH AN UNINTERRUPTED GRATED FIRST POLY AND FIRST CONTACT PATTERNS IN A BIT CELL ARRAY - An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in SRAM cells. Strap rows of the SRAM containing well ties and/or substrate taps which have SRAM cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps. | 11-06-2014 |