| Patent application number | Description | Published |
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| 20090314344 | Solar Cell Production Using Non-Contact Patterning And Direct-Write Metallization - Photovoltaic devices (i.e., solar cells) are formed using non-contact patterning apparatus (e.g., a laser-based patterning systems) to define contact openings through a passivation layer, and direct-write metallization apparatus (e.g., an inkjet-type printing or extrusion-type deposition apparatus) to deposit metallization into the contact openings and over the passivation surface. The metallization includes two portions: a contact (e.g., silicide-producing) material is deposited into the contact openings, then a highly conductive metal is deposited on the contact material and between the contact holes. The device wafers are transported between the patterning and metallization apparatus in hard tooled registration using a conveyor mechanism. Optional sensors are utilized to align the patterning and metallization apparatus to the contact openings. An extrusion-type apparatus is used to form grid lines having a high aspect central metal line that is supported on each side by a transparent material. | 12-24-2009 |
| 20100099220 | ELECTRONIC DEVICE WITH UNIQUE ENCODING - An electronic device comprising a thin film transistor (TFT) array and manufacturing methods thereof according to various embodiments. Jet-printed material is deposited on selected partially formed transistors to form completed transistors. Thus, a selected number of the TFTs are connected into the circuit while the remainder of the TFTs are not connected. An electronic read-out of the array identifies the specific array by distinguishing the connected TFTs from the unconnected ones. For a TFT array with n elements there are 2 | 04-22-2010 |
| 20100317159 | Vertical Coffee-Stain Method For Forming Self-Organized Line Structures - A “vertical” coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a target structure in a solution made up of a fine particle solute dispersed in a liquid solvent such that a “waterline” is formed by the upper (liquid/air) surface of the solution on a targeted linear surface region of the substrate. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the straight-line portion of the substrate surface contacted by the receding waterline. The substrate and staining solution are selected such that the liquid solvent has a stronger attraction to the substrate surface than to itself to produce the required pinning and upward curving waterline. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices. | 12-16-2010 |
| 20100317160 | HORIZONTAL COFFEE-STAIN METHOD USING CONTROL STRUCTURE TO PATTERN SELF-ORGANIZED LINE STRUCTURES - A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices. | 12-16-2010 |
| 20110095342 | Printed Material Constrained By Well Structures And Devices Including Same - A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g., an operative transistor. | 04-28-2011 |
| Patent application number | Description | Published |
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| 20100127268 | THIN FILM TRANSISTORS AND HIGH FILL FACTOR PIXEL CIRCUITS AND METHODS FOR FORMING SAME - A method and structures to achieve improved TFTs and high fill-factor pixel circuits are provided. This system relies on the fact that jet-printed lines have print accuracy, which means the location and the definition of the printed lines and dots is high. The edge of a printed line is well defined if the printing conditions are optimized. This technique utilizes the accurate definition and placement of the edges of printed lines of conductors and insulators to define small features and improved structures. | 05-27-2010 |
| 20100127269 | METHOD AND STRUCTURE FOR ESTABLISHING CONTACTS IN THIN FILM TRANSISTOR DEVICES - The roughness and structural height of printed metal lines is used to pin a fluid. This fluid deposits a top contact material which is connected to the bottom printed contacts through pinholes in the hydrophobic polymer layer. This results in a sandwich-like contact structure achieved in a self-aligned deposition process and having improved source-drain contact for all-additive printed circuits. In one form, the present technique is used for thin film transistor applications, but it may be applied to electrodes in general. | 05-27-2010 |
| 20100127271 | ELECTRONIC CIRCUIT STRUCTURE AND METHOD FOR FORMING SAME - A thin film transistor (TFT) structure is implemented. This embodiment is much less sensitive than conventional TFTs to alignment errors and substrate distortion. In such a configuration, there is no need to define gate features, so the layout is simplified. Moreover, the gate layer may be patterned by several inexpensive printing or non-printing methods. | 05-27-2010 |
| 20100148232 | SURFACE TREATMENT OF HYDROPHOBIC FERROELECTRIC POLYMERS FOR PRINTING - An embodiment is a method and apparatus to treat surface of polymer for printing. Surface of a polymer having a surface energy modified for a time period to control a feature characteristic and/or provide a hysteresis behavior. A material is printed on the surface to form a circuit pattern having at least one of the controlled feature characteristic and the hysteresis behavior. | 06-17-2010 |
| 20110027946 | Horizontal Coffee-Stain Method Using Control Structure To Pattern Self-Organized Line Structures - A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices. | 02-03-2011 |
| 20110147742 | Thin Film Field Effect Transistor with Dual Semiconductor Layers - A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained. | 06-23-2011 |
