| Patent application number | Description | Published |
|---|
| 20090072234 | Test Stuctures for development of metal-insulator-metal (MIM) devices - In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto. | 03-19-2009 |
| 20090154246 | PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS - Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed. | 06-18-2009 |
| 20090212283 | Diode and resistive memory device structures - In an electronic device, a diode and a resistive memory device are connected in series. The diode may take a variety of forms, including oxide or silicon layers, and one of the layers of the diode may make up a layer of the resistive memory device which is in series with that diode. | 08-27-2009 |
| 20100051897 | DEVICE AND PROCESS OF FORMING DEVICE WITH DEVICE STRUCTURE FORMED IN TRENCH AND GRAPHENE LAYER FORMED THEREOVER - A graphene-based device is formed with a substrate having a trench therein, a device structure on the substrate and within the trench, a graphene layer over the device structure, and a protective layer over the graphene layer. Fabrication techniques include forming a trench in a substrate, forming a device structure within the trench, forming a graphene layer over the device structure, and forming a protective layer over the graphene layer. | 03-04-2010 |
| 20100051960 | DEVICE AND PROCESS OF FORMING DEVICE WITH PRE-PATTERNED TRENCH AND GRAPHENE-BASED DEVICE STRUCTURE FORMED THEREIN - A graphene-based device is formed with a trench in one or more layers of material, a graphene layer within the trench, and a device structure on the graphene layer and within the trench. Fabrication techniques includes forming a trench defined by one or more layers of material, forming a graphene layer within the trench, and forming a device structure on the graphene layer and within the trench. | 03-04-2010 |
| 20100055388 | SIDEWALL GRAPHENE DEVICES FOR 3-D ELECTRONICS - A device is provided that includes a structure having a sidewall surface, a layer of material provided on the sidewall surface, and a device structure provided in contact with the layer of material. Fabrication techniques includes a process that includes forming a structure having a sidewall surface, forming a layer of material on the sidewall surface, and forming a device structure in contact with the layer of material, where the device structure and the layer of material are components of a device. | 03-04-2010 |
| 20100055577 | PROCESS OF PATTERNING SMALL SCALE DEVICES - A process is provided that includes forming a first mask on an underlying layer, where the mask has two adjacent portions with an open gap therebetween, and depositing a second mask material within the open gap and at an inclined angle with respect to an upper surface of the underlying layer to form a second mask. In another implementation, a process is provided that includes forming a first mask on an underlying layer, where the mask has a pattern that includes an open gap, and depositing a second mask material within the open gap to form a second mask, where particles of the second mask material are directed in parallel or substantially in parallel to a line at an inclined angle with respect to an upper surface of the underlying layer. | 03-04-2010 |
| 20110147709 | SIGNAL CONTROL ELEMENTS IN FERROMAGNETIC LOGIC - A chain of field coupled nanomagnets includes at least one elements having substantially different anisotropy energy from that of the other nanomagnets. A signal can propagate from a first input nanomagnet having a relatively high anisotropy energy through the chain to an output nanomagnet. The output nanomagnet may have a relatively lower anisotropy energy than the other nanomagnets. Signal flow direction thus can be controlled. The higher anisotropy energy nanomagnet may be attained by use of a ferromagnet material having a higher anisotropy constant and/or configured with a larger volume than the other elements. The lower anisotropy energy magnet may be attained by use of a ferromagnet material having a lower anisotropy constant and/or configured with a smaller volume than the other elements. Logic signal flow control can also be attained making use of three dimensional geometries of nanomagnets with two different orientations. | 06-23-2011 |
