Patent application number | Description | Published |
20150155339 | METHOD OF MAKING ORGANIC LIGHT EMITTING DIODE ARRAY - A method of making organic light emitting diode array includes following steps. A base having a number of first electrodes on a surface of the base is provided. A first organic layer is located on the surface of the base to cover the number of first electrodes. A first organic light emitting layer is applied on the first organic layer. A template with a first patterned surface with a number of grooves with different depths is provided. The template is attached on the first organic light emitting layer and separated from each other, wherein a number of protruding structures with different heights is formed. A second organic light emitting layer is deposited on a part of the plurality of protruding structures. A second organic layer is located on the organic light emitting layer. A second electrode is applied to electrically connect to the second organic layer. | 06-04-2015 |
20150155493 | METHOD OF MAKING ORGANIC LIGHT EMITTING DIODE ARRAY - A method of making organic light emitting diode array includes following steps. A base having a number of first electrodes on a surface of the base is provided. A first organic layer is located on the surface of the base to cover the first electrodes. A template with a first patterned surface is provided, wherein the first patterned surface includes a number of grooves with different depths. The first patterned surface of the template is attached on the first organic layer and separated from each other, wherein a number of protruding structures with different heights is formed. An organic light emitting layer is deposited to cover the protruding structures. A second organic layer is located on the organic light emitting layer. A second electrode is applied to electrically connected to the second organic layer. | 06-04-2015 |
20150179711 | ORGANIC LIGHT EMITTING DIODE ARRAY - The disclosure relates to an organic light emitting diode array. The organic light emitting diode array includes a base defining a number of convexities spaced from each other, a number of first electrodes located on the convexities, a number of electroluminescent layers located on the first electrodes, a patterned second insulative layer located among the convexities to cover part of the base and expose the electroluminescent layers, and a number of second electrodes electrically connected to the electroluminescent layers. The first electrodes are parallel with each other and extend along a first direction. The second electrodes are parallel with each other and extend along a second direction different from the first direction. | 06-25-2015 |
20150179712 | METHOD FOR MAKING ORGANIC LIGHT EMITTING DIODE ARRAY - The disclosure relates to a method of making organic light emitting diode array. A base defining a plurality of convexities is provided. A number of first electrodes are applied on the plurality of convexities. At least one hole injection layer is applied on the first electrodes. A number of hole transport layers are transfer printed on the at least one hole injection layer. Three of the hole transport layers, that correspond to the same pixel unit, have different thickness. A number of electroluminescent layers are applied on the hole transport layers. A patterned second insulative layer is made among the convexities to expose the electroluminescent layers. A second electrode is electrically connected to the electroluminescent layers. | 06-25-2015 |
20150179715 | ORGANIC LIGHT EMITTING DIODE ARRAY - The disclosure relates to an organic light emitting diode array. The organic light emitting diode array includes a number of thin-film transistors arranged to form an array, a first insulative layer, a plurality of first electrodes, a number of electroluminescent layers, a patterned second insulative layer, and at least one second electrode. The first insulative layer is located on the plurality of first electrodes defines a number of convexities. The first electrodes are located on the convexities and electrically connected to the thin-film transistors. The electroluminescent layers are located on the first electrodes. The patterned second insulative layer is located on the first insulative layer to cover the first electrodes and expose the electroluminescent layers. The at least one second electrode is electrically connected to the electroluminescent layers. | 06-25-2015 |
20150179723 | METHOD FOR MAKING ORGANIC LIGHT EMITTING DIODE ARRAY - The disclosure relates to a method of making organic light emitting diode array. A base defining a number of convexities is provided. A number of first electrodes are applied on the number of convexities. A number of electroluminescent layers are transfer printed on the number of first electrodes to form the number of organic light emitting layers. A patterned second insulative layer is made to cover the number of first electrodes and expose the number of organic light emitting layers. A second electrode is electrically connected to the number of organic light emitting layers. | 06-25-2015 |
20150179944 | METHOD FOR MAKING ORGANIC LIGHT EMITTING DIODE ARRAY - The disclosure relates to a method of making organic light emitting diode array. A base defining a plurality of convexities is provided. A number of first electrodes are applied on the plurality of convexities. A number of red light electroluminescent layers are transfer printed on a first group of the first electrodes. A number of green light electroluminescent layers are transfer printed on a second group of the first electrodes. A number of blue light electroluminescent layers are transfer printed on a third group of the first electrodes. A patterned second insulative layer is made to cover the number of first electrodes and expose the electroluminescent layers. A second electrode is electrically connected to the electroluminescent layers. | 06-25-2015 |
20150179945 | METHOD FOR MAKING ORGANIC LIGHT EMITTING DIODE ARRAY - The disclosure relates to a method of making organic light emitting diode array. A base defining a number of convexities is provided. Three of the convexities, that correspond to the same pixel unit, have different heights. A number of first electrodes are applied on the number of convexities. A number of electroluminescent layers are transfer printed on the number of first electrodes to form the number of organic light emitting layers. A patterned second insulative layer is made to cover the number of first electrodes and expose the number of organic light emitting layers. A second electrode is electrically connected to the number of organic light emitting layers. | 06-25-2015 |
20150179946 | METHOD FOR MAKING ORGANIC LIGHT EMITTING DIODE ARRAY - The disclosure relates to a method of making organic light emitting diode array. A base defining a plurality of convexities is provided. A number of first electrodes are applied on the plurality of convexities. A patterned second insulative layer is made among the convexities to cover first parts of the first electrodes between the convexities and expose second parts of the first electrodes on top surfaces of the convexities to form a number of protrudent portions. A number of electroluminescent layers are transfer printed on the number of protrudent portions to form a number of organic light emitting layers. A second electrode is electrically connected to the number of organic light emitting layers. | 06-25-2015 |
Patent application number | Description | Published |
20120236942 | Method and Apparatus for Deriving Temporal Motion Vector Prediction - A method and apparatus for deriving a temporal motion vector predictor (MVP) are disclosed. The MVP is derived for a current block of a current picture in Inter, or Merge, or Skip mode based on co-located reference blocks of a co-located block and a flag is used to indicate the co-located picture. More than one co-located reference blocks can be used to derive the temporal MVP and the co-located reference blocks can be selected from the co-located block as well as neighboring blocks of the co-located block. A search set comprises search motion vectors associated with the co-located reference block(s) is formed. The search motion vector (MV) corresponding to the co-located reference block in the same reference list is searched before the search MV in a different reference list. Various schemes to accommodate implicit method of deriving co-located picture are also disclosed. | 09-20-2012 |
20140169478 | METHOD AND APPARATUS OF DEBLOCKING FILTER WITH SIMPLIFIED BOUNDARY STRENGTH DECISION - A method and apparatus for deblocking of reconstructed video in a video coding system are disclosed. Embodiments according to the present invention determine boundary strength between two blocks without checking whether the block boundary is a coding unit (CU) boundary. In one embodiment according to the present invention, the method comprises determining whether any of the two blocks is Intra coded. If any of the two blocks is Intra coded, the boundary strength is assigned a first value. Otherwise, additional decision processing is performed to determine the boundary strength. In another embodiment, said determining the boundary strength for the block boundary comprises determining whether the block boundary is a TU boundary and whether any of the two blocks contains coefficients. In yet another embodiment, said determining the boundary strength for the block boundary comprises determining whether the two blocks have different reference pictures or different motion vectors. | 06-19-2014 |
20140211848 | METHOD AND APPARATUS FOR REDUCTION OF DEBLOCKING FILTER - A method and apparatus for deblocking of reconstructed video are disclosed. In one embodiment, the method divides a block boundary into two sub-boundaries and separates lines or column across the sub-boundaries into two groups. The deblocking filter decision for each group is determined based on the lines or columns in the respective group. In another embodiment, the method divides block edges of blocks in the LCUs into two edge groups, where the first edge group corresponds to horizontal block edges between two LCUs and the second edge group corresponds to remaining block edges not included in the first edge group. The number of lines processed by a vertical filter in the first edge group is less than the number of lines processed by a vertical filter in the second edge group. Accordingly, a system embodying the present invention has reduced storage requirement. | 07-31-2014 |
20150022633 | METHOD OF FAST ENCODER DECISION IN 3D VIDEO CODING - Multi-view video encoding using early Merge mode decision and/or early CU split termination is disclosed. The present invention encodes a current coding block using the Merge/Skip mode without evaluating coding performance for at least one of Inter modes and Intra modes if the coding conditions associated with the current coding block and a neighboring block set of the current coding block are asserted. The coding conditions may correspond to whether the coding performance of the Skip mode is better than the coding performance of 2N×2N Merge mode for the current coding block and whether all blocks in the neighboring block set select the Merge mode or the Skip mode. Similarly, the process of splitting the current coding block into smaller coding blocks can be terminated without evaluating coding performance associated with the smaller coding blocks from splitting the current coding block if some coding conditions are asserted. | 01-22-2015 |
20150030067 | METHOD AND APPARATUS FOR CODED BLOCK FLAG CODING IN HIGH EFFICIENCY VIDEO CODING - A method and an apparatus for decoding of a video bitstream are disclosed. In one embodiment, the method comprises: decoding a first coded block flag (cbf) of the color component indicating whether a current coding unit (CU) of the color component has at least one non-zero transform coefficient ( | 01-29-2015 |
20150110180 | METHOD AND APPARATUS FOR INTRA TRANSFORM SKIP MODE - A method and apparatus for video coding including an Intra transform Skip mode is disclosed. When the transform Skip mode is ON for a transform unit, embodiments according to the present invention apply different coding processes to the transform unit. The coding process with the transform Skip mode ON uses a different scan pattern from the coding process with the transform Skip mode OFF. According to various embodiments, the transform Skip mode is enabled when the transform unit size is 4×4, the prediction unit and the transform unit having the same size, or the prediction unit uses an INTRA_N×N mode. When the transform Skip mode is enabled, a flag can be signaled in the bitstream to indicate the transform Skip mode selection. Furthermore, the flag can be incorporated in a picture level, a slice level or a sequence level of the video bitstream. | 04-23-2015 |
20150189323 | Method of Three-Dimensional and Multiview Video Coding Using a Disparity Vector - A method and apparatus for a three-dimensional or multi-view video encoding or decoding system are disclosed, where a three-dimensional coding tool relying on a disparity vector are adaptively applied depending on whether the inter-view reference picture pointed by the disparity vector is in the reference list associated with the current slice. The three-dimensional coding tool may correspond to the Inter-View Motion Prediction (IVMP) or View Synthesis Prediction (VSP). If the inter-view reference picture pointed by the DV is not in the current reference list associated with the current slice, the selected three-dimensional coding tool is disabled for the current block. If the inter-view reference picture pointed by the DV is in the current reference list associated with the current slice, the selected three-dimensional coding tool can be applied to the current block. | 07-02-2015 |
20150195570 | Method of Texture Dependent Depth Partition - A method of improved texture-partition-dependent depth partition is disclosed. First, the available texture partitions for a collocated texture block are classified into two or more groups, and a set of candidate depth partitions is determined for each group. In one embodiment, at least one set of the candidate depth partitions contain more than one candidate depth partition and less than all candidate depth partitions. In another embodiment, the collocated texture blocks are classified into two groups, and one of the two groups includes the N×N texture partition and at least another texture partition. In yet another embodiment, the collocated texture blocks are classified into three groups or more. A current depth partition for the current depth block is then selected from a corresponding set of candidate depth partitions according to a corresponding group that a current texture partition associated with the collocated texture block belongs. | 07-09-2015 |
20150201215 | METHOD OF CONSTRAIN DISPARITY VECTOR DERIVATION IN 3D VIDEO CODING - A method for three-dimensional video encoding or decoding are disclosed. In one embodiment, the method constrains the disparity vector (DV) to generate a constrained DV, wherein horizontal, vertical, or both components of the constrained DV is constrained to be zero or within a range from M to N units of DV precision, and M and N are integers. In another embodiment, a derived DV for DV based motion-compensated-prediction is determined from a constrained neighboring block set of the current block. In yet another embodiment, a derived disparity vector is derived to replace an inter-view Merge candidate if the inter-view Merge candidate of the current block is not available or not valid. In yet another embodiment, a DV difference (DVD) or a motion vector difference (MVD) for the current block is determined according to a DV and the DVD/MVP is constrained to be zero or within a range. | 07-16-2015 |
20150237324 | Method of Depth Based Block Partitioning - A method of simplified depth-based block partitioning (DBBP) for three-dimensional and multi-view video coding is disclosed. In one embodiment, the derivation of a representative value of a corresponding depth block or a reference texture block in a reference view for generating a segmentation mask and selecting a block partition are unified. In another embodiment, the first representative value, the second representative value, or both are calculated from partial samples of the corresponding depth block or the reference texture block. In yet another embodiment, a first representative value for first samples in a first partitioned block of the corresponding depth block or the reference texture block, and a second representative value for second samples in a second partitioned block of the corresponding depth block or the reference texture block for each of block partition candidates are determined. | 08-20-2015 |
20150264347 | METHOD AND APPARATUS OF MOTION VECTOR DERIVATION 3D VIDEO CODING - A method and apparatus for three-dimensional and multi-view video coding are disclosed, where the motion vector (MV) or disparity vector (DV) candidate list construction process for a block depends on whether the target reference picture corresponds to an inter-view reference picture or whether the inter-view candidate refers to an inter-view reference picture. In one embodiment, an MV or DV candidate list for a block coded in Merge mode is constructed, and an inter-view candidate in the MV or DV candidate list is set lower than the first candidate position if the inter-view candidate refers to an inter-view reference picture. In another embodiment, an MV or DV candidate list for a block coded in advanced motion vector prediction mode is constructed, and an inter-view candidate is set lower than the first candidate position if the inter-view candidate refers to an inter-view reference picture. | 09-17-2015 |
20150304681 | METHOD AND APPARATUS OF INTER-VIEW MOTION VECTOR PREDICTION AND DISPARITY VECTOR PREDICTION IN 3D VIDEO CODING - A method and apparatus for deriving inter-view candidate for a block in a picture for three-dimensional video coding are disclosed. Embodiments of the present invention derive the inter-view candidate from an inter-view collocated block in an inter-view picture corresponding to the current block of the current picture, wherein the inter-view picture is an inter-view reference picture and wherein the inter-view reference picture is in a reference picture list of the current block. The derived inter-view candidate is then used for encoding or decoding of the current motion vector or disparity vector of the current block. One aspect of the invention addresses re-use of the motion information of the inter-view collocated block. Another aspect of the invention addresses constrains on the inter-view picture that can be used to derive the inter-view candidate. | 10-22-2015 |
20150341663 | METHOD AND APPARATUS FOR RESIDUAL PREDICTION IN THREE-DIMENSIONAL VIDEO CODING - A method and apparatus using pseudo residues to predict current residues for three-dimensional or multi-view video coding are disclosed. The method first receives input data associated with a current block of a current picture in a current dependent view and determines an inter-view reference block in a first inter-view reference picture in a reference view according to a DV (disparity vector), where the current picture and the first inter-view reference picture correspond to same time instance. Pseudo residues are then determined and used for encoding or decoding of the current block, where the pseudo residues correspond to differences between a corresponding region in an inter-time reference picture in the current dependent view and a pseudo reference region in a pseudo reference picture in the reference view, and where the inter-time reference picture and the pseudo reference picture correspond to same time instance. | 11-26-2015 |
20150341664 | METHOD AND APPARATUS OF DISPARITY VECTOR DERIVATION IN THREE-DIMENSIONAL VIDEO CODING - A derived disparity vector is determined based on spatial neighboring blocks and temporal neighboring blocks of the current block. The temporal neighboring blocks are searched according to a temporal search order and the temporal search order is the same for all dependent views. Any temporal neighboring block from a CTU below the current CTU row may be omitted in the temporal search order. The derived DV can also be used for predicting a DV of a DCP (disparity-compensated prediction) block for the current block in the AMVP mode, the Skip mode or the Merge mode. The temporal neighboring blocks may correspond to a temporal CT block and a temporal BR block. In one embodiment, the temporal search order checks the temporal BR block first and the temporal CT block next. | 11-26-2015 |
20160021393 | Method of Error-Resilient Illumination Compensation for Three- Dimensional Video Coding - A method of illumination compensation for three-dimensional or multi-view encoding and decoding. The method incorporates an illumination compensation flag only if the illumination compensation is enabled and the current coding unit is processed by one 2N×2N prediction unit. The illumination compensation is applied to the current coding unit according to the illumination compensation flag. The illumination compensation flag is incorporated when the current coding unit is coded in Merge mode without checking whether a current reference picture is an inter-view reference picture. | 01-21-2016 |
20160050435 | Method of Texture Merging Candidate Derivation in 3D Video Coding - A method of depth map coding for a three-dimensional video coding system incorporating consistent texture merging candidate is disclosed. According to the first embodiment, the current depth block will only inherit the motion information of the collocated texture block if one reference depth picture has the same POC (picture order count) and ViewId (view identifier) as the reference texture picture of the collocated texture block. In another embodiment, the encoder assigns the same total number of reference pictures for both the depth component and the collocated texture component for each reference list. Furthermore, the POC (picture order count) and the ViewId (view identifier) for both the depth image unit and the texture image unit are assigned to be the same for each reference list and for each reference picture. | 02-18-2016 |
20160100190 | Method of View Synthesis Prediction in 3D Video Coding - A method and apparatus for three-dimensional or multi-view video encoding and decoding using VSP (view synthesis prediction) with uniform sub-block partition are disclosed. For a current texture block comprising multiple partition blocks, the system derives a single partition decision and partitions each partition block of the current texture block into multiples sub-blocks according to the single partition decision. The VSP processing is then applied to each sub-block to derive the inter-view prediction using VSP. The single partition decision is derived using depth samples of the depth block in a reference view. | 04-07-2016 |
Patent application number | Description | Published |
20080213657 | High Capacity Lithium Ion Secondary Battery with Metal Case - The present invention relates to a high capacity lithium ion secondary battery with metal casing, characterized in that each of the positive terminal or negative terminal includes respectively an upper backing plate, an upper insulator and a lower insulator. The upper backing plate and upper insulator are long-circular piece, two or more rivets pass through the concentric holes on the upper arm of a positive or negative electrode tab, the lower insulator, a sealing cover, the upper insulator and the upper backing plate respectively and rivet them as a whole. The lower arm of the positive electrode tab or negative electrode tab is connected to the corresponding positive or negative electrode tab on a battery core body, and the battery core body is comprised of two or more winded cores in parallel connection. The battery is provided with the advantages and effects of good sealing performance, good electrochemistry property, and simple manufacturing process, as well as high security of a pile comprised of plurality of such individual batteries. As a result the useless space in height of battery is reduced and the volumetric specific energy of the same is enhanced. | 09-04-2008 |
20090111014 | Liquid State Lithium Ion Battery with Aluminum-Plastic Complex Film - A liquid state lithium ion battery with aluminum-plastic complex film includes an electrode assembly made up of anodes ( | 04-30-2009 |
20090123833 | LITHIUM ION BATTERY - A lithium ion battery characterized in that a porous elastomer made of non-metal material is provided among the positive and negative electrodes groups, or between the electrodes groups and the inner wall of the shell and the elastomer is in the shape of sheet or stick. The thickness of the elastomer is 0.5 mm-5.0 mm, and the porosity is 10%-80%. The said battery can avoid effectively the expansion of the shell during the cycle of charge and discharge, and can be processed conveniently, and the cyclic life and safety property of the battery can be improved effectively. | 05-14-2009 |
20090233166 | LITHIUM-ION BATTERY WITH MEDIUM AND SMALL CAPACITY AND HIGH OUTPUT - A lithium-ion battery with medium and small capacity and high output, comprises a shell, a cell core and electrolyte located in the shell; the said cell core obtained by winding anode sheets, cathode sheets and separators between the anode sheets and cathode sheets, the said anode sheets coated with anode active material, the said cathode sheets coated with cathode active material; the said anode active material includes LiMn | 09-17-2009 |
Patent application number | Description | Published |
20150028341 | Array Substrate, Display Device, and Method for Manufacturing the Array Substrate - An array substrate includes a substrate and data lines and scan lines arranged on the substrate, The data lines and the scan lines define plural pixel regions. A thin film transistor is arranged in each pixel region and includes a gate electrode, a source electrode, a drain electrode, and an active region. The gate electrode is arranged above the active region. The source electrode and the drain electrode are arranged at two opposite sides of the active region respectively. A light shielding metal layer is further arranged in each pixel region. The light shielding metal layer and the data lines are arranged in the same layer on the substrate. The light shielding metal layer is arranged under the active region and at least partially overlaps with the active region. The data line is close to the source electrode and does not overlap with the active region at least partially. | 01-29-2015 |
20150311232 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - The invention discloses an array substrate and a manufacturing method thereof and a display device, which can solve the problems such as complicated, high cost, time-consuming process in the prior art, and increase the storage capacitance. In the array substrate, data lines and a common electrode line are provided in the same layer on the base substrate and below an active layer, the data lines and the common electrode line are provided separately, the common electrode is provided with a connection part which partly overlaps with the common electrode line in an orthographic projection direction, and the common electrode is electrically connected to the common electrode line through a first via between the connection part and the common electrode line. | 10-29-2015 |
20150317023 | Capacitive in-cell touch panel and display device - The invention discloses a capacitive in-cell touch panel and a display device. Since at least two neighboring gate lines on a common array substrate and the gates connected with them serve as a first touch sensing electrode, at least two neighboring data lines on the common array substrate and the sources connected with them serve as a second touch sensing electrode, and there is no need to further add a new film layer on the existing array substrate, this may reduce the number of masking in the production process, decrease the thickness of the touch panel and lower the production cost; moreover, a time divisional driving mode is adopted in the touch-control time period and the display time period, which may avoid the interference between the display signal and the touch-control driving signal, and guarantee the quality of a display picture and the accuracy of the touch-control. | 11-05-2015 |
20150325188 | Array Substrate and Display Panel - The present invention provides an array substrate and a display panel. The array substrate comprises a plurality of data lines and a plurality of common electrode lines, wherein, the array substrate further comprises at least one discharge unit, each discharge unit corresponds to one of the plurality of data lines and is connected between the corresponding data line and one of the plurality of common electrode lines, and each discharge unit can selectively conduct the data line to the common electrode line connected thereto. The display panel comprises the array substrate. In the present invention, the discharge unit can selectively conduct the data line connected thereto to the common electrode line connected thereto, to enable fast discharge of the storage capacitance and reduce occurrence of afterimage phenomenon. | 11-12-2015 |
20150339959 | PANEL FUNCTION TEST CIRCUIT, DISPLAY PANEL, AND METHODS FOR FUNCTION TEST AND ELECTROSTATIC PROTECTION - A panel function test circuit is able to perform a function test when a display panel is in a first state and is able to perform electrostatic protection when the display panel is in a second state, whereby the display panel requires fewer components and less wiring space. | 11-26-2015 |
Patent application number | Description | Published |
20150060863 | ARRAY SUBSTRATE, METHOD FOR FABRICATING THE SAME AND DISPLAY DEVICE - An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate includes a base substrate, and further includes a metal shield layer, a semiconductor layer, a gate insulation layer, a gate metal layer, an interlayer dielectric layer, a source-drain metal layer and a pixel electrode layer sequentially formed on the base substrate. At least one first via hole penetrating to the metal shield layer is formed in the interlayer dielectric layer and the gate insulation layer. The source-drain metal layer is formed in the at least one first via hole and on the interlayer dielectric layer having the at least one first via hole. | 03-05-2015 |
20150243237 | SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DISPLAY APPARATUS - The present disclosure relates to the technical field of display. Provided are a shift register unit, a gate driving circuit and a display apparatus, the shift register unit includes an inputting module, a first outputting module and a second outputting module. As compared with the prior art, the structure of the shift register unit can be simplified effectively, and the number of use of the transistors can be further reduced. Embodiments of the present disclosure are used to implement scanning and driving. | 08-27-2015 |
20150325170 | METHOD, APPARATUS AND SYSTEM FOR DISPLAY COMPENSATION - A method, an apparatus and a system for display compensation relate to the field of display technique. The method for display compensation includes: measuring luminance of each of pixels in a full-color test picture outputted from a display apparatus in a uncompensated status when the display apparatus outputs the full-color test picture; obtaining a reference luminance value according to the measured luminance values of the respective pixels; obtaining compensation coefficients for the respective pixels according to the reference luminance value and the luminance values of the respective pixels; performing a compensation and correction on signals inputted to the respective pixels respectively according to the compensation coefficients. By utilizing the method, the issue of the non-uniformity of the display effect in the display apparatus can be addressed effectively. | 11-12-2015 |
20160027371 | SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DISPLAY DEVICE - There provide a shift register unit, a gate driving circuit and a display device, The shift register unit includes an input module, an output module, a pulling-down driving module, a pulling-down module and a resetting module. The input module is connected to a first input signal terminal, a first direct current signal terminal, a second input signal terminal and a second direct current signal terminal respectively. The output module is connected to a first clock signal terminal. The pulling-down driving module is connected to the first clock signal terminal, a second clock signal terminal and a low voltage signal terminal. The pulling-down module is connected to the low voltage signal terminal. The resetting module is connected to the second clock signal terminal and the low voltage signal terminal respectively. The noise of the shift register unit can be reduced and the stability of the shift register unit can be enhanced. | 01-28-2016 |
20160035281 | ARRAY SUBSTRATE AND DISPLAY APPARATUS - There are provided an array substrate and a display apparatus. The array substrate comprises a voltage driving circuit ( | 02-04-2016 |
Patent application number | Description | Published |
20110270886 | MECHANISM AND APPARATUS FOR TRANSPARENTLY ENABLES MULTI-TENANT FILE ACCESS OPERATION - The present invention relates to a multi-tenant technology. The disclosure provides a method for processing a file access request to a multi-tenant application by using a file proxy and a corresponding file proxy apparatus, the method comprising: intercepting a file access request; converting the file access request based on a predetermined file isolation model; and transmitting the converted file access request to an operating system. By using this invention, the necessity of modifying a source code of an application so as to enabling a single-tenant application to support an operation in the multi-tenant model may be reduced. The present invention further provides a multi-tenant file system adapted for a multi-tenant application. In cooperation with the multi-tenant system, the method and file proxy apparatus according to the present invention may provide transparent support to fulfill security isolation and access control of tenant files with different SLAs. | 11-03-2011 |
20120030192 | APPARATUS FOR PROCESSING MATERIALIZED TABLES IN A MULTI-TENANT APPLICATION SYSTEM - A method, system and computer program for processing materialized tables in a multi-tenant application system, wherein in the multi-tenant application system, a plurality of tenants share one or more basic-tables. According to the data access history information of the plurality of tenants, an update pattern analyzer analyzes the similarity of the update patterns for one or more basic-tables by the plurality of tenants. Furthermore, according to the similarity analyzed by the update pattern analyzer, a tenant grouping means groups the plurality of tenants into a plurality of tenant groups. Additionally, according to the tenant groups grouped by the tenant grouping means, a materialized table constructor constructs the tenant group materialized tables from the one or more basic-tables. | 02-02-2012 |
20130055203 | LOCATING ISOLATION POINTS IN AN APPLICATION UNDER MULTI-TENANT ENVIRONMENT - A computer implemented method for locating isolation points in an application under multi-tenant environment includes scanning, using a computer device an application by using scanning rules, to obtain potential isolation points and relationships between the potential isolation points; specifying at least one isolation point among the potential isolation points; and screening an isolation point from the potential isolation points by using relationships between the specified at least one isolation point and the remaining potential isolation points. | 02-28-2013 |
20130055204 | LOCATING ISOLATION POINTS IN AN APPLICATION UNDER MULTI-TENANT ENVIRONMENT - An apparatus for locating isolation points in an application under multi-tenant environment includes a scanning module configured to scan the application, by using scanning rules, to obtain potential isolation points and relationships between the potential isolation points; a specifying module configured to specify at least one isolation point among the potential isolation points; and an isolation point screening module configured to screen an isolation point from the potential isolation points by using relationships between the specified at least one isolation point and the remaining potential isolation points. | 02-28-2013 |
20130139172 | CONTROLLING THE USE OF COMPUTING RESOURCES IN A DATABASE AS A SERVICE - A method and apparatus controls use of a computing resource by multiple tenants in DBaaS service. The method includes intercepting a task that is to access a computer resource, the task being an operating system process or thread; identifying a tenant that is in association with the task from the multiple tenants; determining other tasks of the tenant that access the computing resource; and controlling the use of the computing resource by the task, so that the total amount of usage of the computing resource by the task and the other tasks does not exceed the limit of usage of the computing resource for the tenant. | 05-30-2013 |
20130222136 | RADIO FREQUENCY IDENTIFICATION TAG GRIPPER DEVICE - The present invention provides a radio frequency identification tag gripper device, the technical scheme including: a first gripper portion; a second gripper portion, which generates a gripping force together with the first gripper portion; a radio frequency identification tag, a circuit portion of which is divided into at least a first section and a second section, an upper surface of the first section and a lower surface of the second section being coated with strong glue, wherein the upper surface of the first section is used to bond with a grip surface of the first gripper portion when gripped tightly, and the lower surface of the second section is used to produce a coupling force with a surface of the gripped object when gripped tightly. Utilizing the technical solution of the present invention, it is possible to further improve the security of monitoring of the radio frequency identification tag. | 08-29-2013 |
20130275044 | METHOD AND APPARATUS FOR TRANSPORTING RESIDUE OF VEHICLE POSITION DATA VIA WIRELESS NETWORK - The invention relates to compressed data transmission in wireless data communication. Disclosed are methods and apparatuses for transporting residue of vehicle position data via a wireless network. A disclosed method for transporting residue of vehicle position data via a wireless network, includes the steps of: receiving data for updating residue encoding schema from a monitoring server; constructing a residue encoding schema based on the data, thereby producing a constructed residue encoding schema; and storing the constructed residue encoding schema such that the constructed residue encoding schema will become the current residue encoding schema; where: the constructed residue encoding schema is constructed such that each residue of the constructed residue encoding schema corresponds to a code; and the constructed residue encoding schema is constructed such that a residue having a relatively high probability of occurrence corresponds to a code of relatively short length. | 10-17-2013 |
20130282906 | MULTI-USER ANALYTICAL SYSTEM AND CORRESPONDING DEVICE AND METHOD - The present invention relates to multi-user analytical system and corresponding device and method. The device includes an interception module configured to intercept a user's request for a first core object, wherein the first core object belongs to core object; a transformation module configured to create, in response to the request being a creation request, the first core object specific to the user; a mapping module configured to interpret, in response to the request being a non-creation request, the request as a request for the first core object specific to the user. The present invention also includes an isolation method for the multi-user analytical system. The technical solutions provided in the present invention can effectively enable multiple users to share physical resources in the analytical system, and the users are isolated from each other in a substantially transparent way. | 10-24-2013 |
20130311480 | SENSOR DATA LOCATING - A method, an apparatus, and a system for locating sensor data. The method includes the steps of: obtaining an index table; intercepting a query for sensor data in runtime; extracting a characteristic parameter from a query condition; locating a block identifier of matching sensor data storage blocks in the index table by using the characteristic parameter; and loading the storage blocks into a memory space of a working processor; where the index table contains mapping relationships between block identifiers of sensor data storage blocks and characteristic attributes of sensor data. | 11-21-2013 |
20140040294 | MANIPULATION OF MULTI-TENANCY DATABASE - Embodiments relate to manipulating a multi-tenant database, wherein the multi-tenant database comprises one or more source databases for storing tenant data. An aspect includes receiving a database operation request for one or more tenant-specific logic views, wherein the tenant-specific logic views are created for respective tenants based on mapping information pointing to the one or more source databases included in the multi-tenant database and multi-tenant metadata. Another aspect includes acquiring the mapping information related to the database operation request and pointing to the one or more source databases included in the multi-tenant database. Yet another aspect includes performing a database operation corresponding to the database operation requested for the one or more source databases based on the acquired mapping information. | 02-06-2014 |
20150213714 | Transporting Residue of Vehicle Position Data Via Wireless Network - The invention relates to compressed data transmission in wireless data communication. Disclosed are methods and apparatuses for transporting residue of vehicle position data via a wireless network. A disclosed method for transporting residue of vehicle position data via a wireless network, includes the steps of: receiving data for updating residue encoding schema from a monitoring server; constructing a residue encoding schema based on the data, thereby producing a constructed residue encoding schema; and storing the constructed residue encoding schema such that the constructed residue encoding schema will become the current residue encoding schema; where: the constructed residue encoding schema is constructed such that each residue of the constructed residue encoding schema corresponds to a code; and the constructed residue encoding schema is constructed such that a residue having a relatively high probability of occurrence corresponds to a code of relatively short length. | 07-30-2015 |
20150215743 | Transporting Residue of Vehicle Position Data Via Wireless Network - The invention relates to compressed data transmission in wireless data communication. Disclosed are methods and apparatuses for transporting residue of vehicle position data via a wireless network. A disclosed method for transporting residue of vehicle position data via a wireless network, includes the steps of: receiving data for updating residue encoding schema from a monitoring server; constructing a residue encoding schema based on the data, thereby producing a constructed residue encoding schema; and storing the constructed residue encoding schema such that the constructed residue encoding schema will become the current residue encoding schema; where: the constructed residue encoding schema is constructed such that each residue of the constructed residue encoding schema corresponds to a code; and the constructed residue encoding schema is constructed such that a residue having a relatively high probability of occurrence corresponds to a code of relatively short length. | 07-30-2015 |
20150215817 | Transporting Residue of Vehicle Position Data Via Wireless Network - The invention relates to compressed data transmission in wireless data communication. Disclosed are methods and apparatuses for transporting residue of vehicle position data via a wireless network. A disclosed method for transporting residue of vehicle position data via a wireless network, includes the steps of: receiving data for updating residue encoding schema from a monitoring server; constructing a residue encoding schema based on the data, thereby producing a constructed residue encoding schema; and storing the constructed residue encoding schema such that the constructed residue encoding schema will become the current residue encoding schema; where: the constructed residue encoding schema is constructed such that each residue of the constructed residue encoding schema corresponds to a code; and the constructed residue encoding schema is constructed such that a residue having a relatively high probability of occurrence corresponds to a code of relatively short length. | 07-30-2015 |
Patent application number | Description | Published |
20120032239 | METHOD FOR INTRODUCING CHANNEL STRESS AND FIELD EFFECT TRANSISTOR FABRICATED BY THE SAME - The present invention relates to CMOS ultra large scale integrated circuits, and provides a method for introducing channel stress and a field effect transistor fabricated by the same. According to the present invention, a strained dielectric layer is interposed between source/drain regions and a substrate of a field effect transistor, and a strain is induced in a channel by the strained dielectric layer which directly contacts the substrate, so as to improve a carrier mobility of the channel and a performance of the device. The specific effects of the invention include: a tensile strain may be induced in the channel by using the strained dielectric layer having a tensile strain in order to increase an electron mobility of the channel; a compressive strain may be induced in the channel by using the strained dielectric layer having a compressive strain in order to increase a hole mobility of the channel. According to the invention, not only an effectiveness of the introduction of channel stress is ensued, but the device structure of the field effect transistor is also improved fundamentally, so that a capability for suppressing a short channel effect of the device is increased. | 02-09-2012 |
20120187495 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present invention provides a semiconductor device and a method for fabricating the same, wherein the method comprises: providing a germanium-based semiconductor substrate having a plurality of active regions and device isolation regions between the plurality of the active regions, wherein a gate dielectric layer and a gate over the gate dielectric layer are provided on the active regions, and the active regions include source and drain extension regions and deep source and drain regions; performing a first ion implantation process with respect to the source and drain extension regions, wherein the ions implanted in the first ion implantation process include silicon or carbon; performing a second ion implantation process with respect to the source and drain extension regions; performing a third ion implantation process with respect to the deep source and drain regions; performing an annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion implantation process. According to the method for fabricating a semiconductor device, through the implantation of silicon impurities, appropriate stress may be introduced into the germanium channel effectively by the mismatch of lattices in the source and drain regions, so that the mobility of electrons in the channel is enhanced and the performance of the device is improved. | 07-26-2012 |
20120190202 | METHOD FOR FABRICATING SEMICONDUCTOR NANO CIRCULAR RING - The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure. | 07-26-2012 |
20120264311 | SURFACE TREATMENT METHOD FOR GERMANIUM BASED DEVICE - The present invention provides a surface treatment method for germanium based device. Through performing surface pretreatment to the germanium based device by using an aqueous solution of ammonium fluoride as a passivant, the interface state may be reduced, the formation of natural oxidation layer at the germanium surface may be inhibited, the regeneration of natural oxidation layer and the out-diffusion of the germanium based substrate material can be effectively inhibited, and the thermal stability of the metal germanide may also be increased significantly, so that the interface quality of the germanium based device is improved easily and effectively, which are advantageous to improve the performance of the germanium based transistor. | 10-18-2012 |
20120289004 | FABRICATION METHOD OF GERMANIUM-BASED N-TYPE SCHOTTKY FIELD EFFECT TRANSISTOR - The present invention discloses a fabrication method of a Ge-based N-type Schottky field effect transistor and relates to a filed of ultra-large-scaled integrated circuit fabrication process. The present invention forms a thin high K dielectric layer between a substrate and a metal source/drain. The thin layer on one hand may block the electron wave function of metal from inducing an MIGS interface state in the semiconductor forbidden band, on the other hand may passivate the dangling bonds at the interface of Ge. Meanwhile, since the insulating dielectric layer has a very thin thickness, and electrons can substantially pass freely, the parasitic resistances of the source and the drain are not significantly increased. The method can weaken the Fermi level pinning effect, cause the Fermi energy level close to the position of the conduction band of Ge and lower the electron barrier, thereby increasing the current switching ratio of the Ge-based Schottky transistor and improve the performance of the NMOS device. | 11-15-2012 |
20130013245 | METHOD FOR OBTAINING DISTRIBUTION OF CHARGES ALONG CHANNEL IN MOS TRANSISTOR - The present invention discloses a method for obtaining a distribution of charges along a channel of a MOS transistor, which is used for obtaining distributions of interface states charges and charges of a gate dielectric layer in the MOS transistor. The method includes: adding a MOS transistor into a test circuit; measuring two charge pumping current curves when a source terminal is open-circuited or when a drain terminal is open-circuited before and after a stress is applied by using a charge pumping current test method, where one of the two charge pumping current curves is an original curve and the other one is an post-stress curve; finding a point B corresponding to a point A on the original curve on the post-stress curve, and estimating amount of locally-generated interface states charges and charges of the gate dielectric layer by a variation of the charge pumping current and a variation in a voltage at a local point. As compared with a conventional method for obtaining a distribution, the method of the present invention can obtain a distribution of charges along a direction form the drain or source terminal to the channel more easily and rapidly, with an aid of a computer. A mass of complicated and repeated tests are reduced. Also, the method can provide an effective base for improving device reliability. | 01-10-2013 |
20130043515 | Strained Channel Field Effect Transistor and the Method for Fabricating the Same - The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device. | 02-21-2013 |
20130069126 | GERMANIUM-BASED NMOS DEVICE AND METHOD FOR FABRICATING THE SAME - An embodiment of the invention provides a germanium-based NMOS device and a method for fabricating the same, which relates to fabrication process technology of an ultra-large-scale-integrated (ULSI) circuit. The germanium-based NMOS device has two dielectric layer interposed between a metal source/drain and a substrate. The bottom dielectric layer includes a dielectric material having a high pinning coefficient S such as hafnium oxide, silicon nitride, hafnium silicon oxide or the like, and the top dielectric layer includes a dielectric material having a low conduction band offset ΔE | 03-21-2013 |
20130103351 | Method for Predicting Reliable Lifetime of SOI Mosfet Device - Disclosed herein is a method for predicting a reliable lifetime of a SOI MOSFET device. The method comprises: measuring a relationship of a gate resistance of the SOI MOSFET device varying as a function of a temperature at different wafer temperatures; performing a lifetime accelerating test on the SOI MOSFET device at different wafer temperatures, so as to obtain a degenerating relationship of a parameter representing the lifetime of the device as a function of stress time, and obtain a lifetime in the presence of self-heating when the parameter degenerates to 10%; performing a self-heating correction on the measured lifetime of the device by using the measured self-heating temperature and an Arrhenius model, so as to obtain a lifetime without self-heating influence; performing a self-heating correction on a variation of the drain current caused by self-heating; performing a self-heating correction on an impact ionization rate caused by hot carriers; and predicting the lifetime of the SOI MOSFET device under a bias. The embodiment of the invention prevents the self-heating effect from affecting the SOI MOSFET device in a practical logic circuit or in an AC analog circuit, which leads to a more precise prediction result. | 04-25-2013 |
20130119445 | CMOS DEVICE FOR REDUCING RADIATION-INDUCED CHARGE COLLECTION AND METHOD FOR FABRICATING THE SAME - A CMOS device for reducing a radiation-induced charge collection and a method for fabricating the same. In the CMOS device, a heavily doped charge collection-suppressed region is disposed directly under the source region and the drain region. The region has a doping type opposite that of the source region and the drain region, and has a doping concentration not less than that of the source region and the drain region. The charge collection-suppressed region has a lateral part slightly less than or equal to that of the source region and the drain region, and has a lateral range toward to the channel not exceed the edges of the source region and the drain region. The CMOS device may greatly reduce a range of the funnel that appears under the action of a single particle, so that charges collected instantaneously under a force of an electric field may be reduced. | 05-16-2013 |
20130161757 | CMOS Device for Reducing Charge Sharing Effect and Fabrication Method Thereof - The present invention discloses a CMOS device of reducing charge sharing effect and a fabrication method thereof. The present invention has an additional isolation for trapping carriers disposed right below an isolation region. the material of the additional isolation region is porous silicon. Since porous silicon is a functional material of spongy structure by electrochemistry anodic oxidizing monocrystalline silicon wafer, there are a large number of microvoids and dangling bonds on the surface layer of the porous silicon. These defects may form defect states in a center of forbidden band of the porous silicon, the defect states may trap carriers so as to cause an increased resistance. And with an increase of density of corrosion current, porosity increases, and defects in the porous silicon increase. The present invention can reduce the charge sharing effect due to heavy ions by using a feature that the defect states in the porous silicon trap carriers, the formation of a shallow trench isolation (STI) region and a isolation region underneath only needs one time photolithography, and the process is simple, so that radioresistance performance of an integrated circuit may be greatly increased. | 06-27-2013 |
20130309875 | INTERFACE TREATMENT METHOD FOR GERMANIUM-BASED DEVICE - Disclosed herein is an interface treatment method for germanium-based device, which belongs to the field of manufacturing technologies of ultra large scaled integrated (ULSI) circuits. In the method, the natural oxide layer on ther surface of the germanium-based substrate is removed by using a concentrated hydrochloric acid solution having a mass percentage concentration of 15%˜36%, and dangling bonds of the surface are performed a passivation treatment by using a diluted hydrochloric acid solution having a mass percentage concentration of 5%˜10% so as to form a stable passivation layer on the surface. This method makes a good foundation for depositing a high-K (high dielectric constant) gate dielectric on the surface of the germanium-based substrate after cleaning and passivating, enhances quality of the interface between the gate dielectric and the substrate, and improves the electrical performance of germanium-based MOS device. | 11-21-2013 |
20140117465 | GE-BASED NMOS DEVICE AND METHOD FOR FABRICATING THE SAME - The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO | 05-01-2014 |
20150014765 | RADIATION RESISTANT CMOS DEVICE AND METHOD FOR FABRICATING THE SAME - A radiation resistant CMOS device and a method for fabricating the same. The CMOS device includes a substrate, a source region, a drain region and a vertical channel on the substrate. A first dielectric protection region is inserted into the vertical channel at the center of the vertical channel to divide the vertical channel into two parts and has a height equal to the length of the vertical channel. The edge of the first dielectric protection region is 20-100 nm from an outer side of the channel, with a central axis of an silicon platform for an active region as the center. A second dielectric protection region is disposed under the source or drain region, with a length equal to the length of the source or drain region and a height of 10-50 nm. The dielectric protection regions effectively block paths for the source and drain regions collecting charges. | 01-15-2015 |
20150031188 | METHOD FOR ISOLATING ACTIVE REGIONS IN GERMANIUM-BASED MOS DEVICE - Disclosed herein is a method for isolating active regions in a germanium-based MOS device. A surface of a germanium-based substrate is covered by a thin polysilicon layer or a poly-SiGe layer, and an isolation structure of germanium dioxide covered by a silicon dioxide layer or a SiGe oxide layer on top is formed by means of two steps of oxidation in a case of the active regions are protected. Such two steps of oxidation using the polysilicon layer or the poly-SiGe layer as a sacrificial layer is advantageous to improve the isolation quality of a fabricated germanium dioxide and to reduce a beak effect occurred during a local field oxygen oxidation so as to dramatically elevate the performance of the germanium device. | 01-29-2015 |
20150179439 | METHOD FOR PROCESSING GATE DIELECTRIC LAYER DEPOSITED ON GERMANIUM-BASED OR GROUP III-V COMPOUND-BASED SUBSTRATE - The present invention discloses a method for processing a gate dielectric layer deposited on a germanium-based or Group III-V compound-based substrate, belonging to a semiconductor device field. The method comprises the steps of depositing a high-K gate dielectric layer on the germanium-based or Group III-V compound-based substrate, and then performing a plasma process to the high-K gate dielectric layer by using fluorine plasma, wherein during the plasma process, a guiding electric field is applied so that fluorine ions, when being accelerated to a surface of the gate dielectric layer, has an energy of | 06-25-2015 |
20150219698 | METHOD FOR SEPARATING THRESHOLD VOLTAGE SHIFTS CAUSED BY TWO EFFECTS IN SOI DEVICE - The present invention discloses a method for separating SOI device threshold voltage shift under a DC HCl stress, which belongs to a semiconductor reliability test field. By means of this method, under the condition that stressing bias is applied simultaneously to a gate terminal and a drain terminal of the SOI PMOSFET, the influences of HCl effect and NBTI effect are separated on the threshold voltage shift under the DC HCl stress. Adopting the present invention helps to better understand degradation mechanisms from HCl effect under stress with V | 08-06-2015 |
20160027911 | A Radiation-Hardened-by-Design (RHBD) Multi-Gate Device and a Fabrication Method Thereof - The present invention discloses a radiation-hardened-by-design (RHBD) multi-gate device and a fabrication method thereof. The multi-gate device of the present invention includes a substrate; a source region and a drain region, which are on the substrate; a protruding fin structure and a field dielectric layer between the source region and the drain region on the substrate; a gate dielectric and a gate electrode on the fin structure and the dielectric layer; and two isolation layers separated to each other, which are disposed in the drain region between the adjacent two fins, wherein an interlayer is sandwiched between the two isolation layers. The interlayer has a doping type which is opposite to that of the substrate so that a shunt PN junction is formed between the interlayer and the substrate, and the shunt PN junction has an electrode not connected to the drain so that a part of the charges collected by the shunt PN junction are not output to the drain and are ultimately guided out of the multi-gate devices, thereby weakening the influence of the single-event effect. In comparison with a multi-gate device of prior art, the multi-gate device of the present invention may effectively suppress the sensitivity of the device to single event irradiation in the event that the layout areas of the two types of devices are almost same. | 01-28-2016 |