Patent application number | Description | Published |
20110172979 | CIRCUIT-LEVEL VALIDATION OF COMPUTER EXECUTABLE DEVICE/CIRCUIT SIMULATORS - A method is disclosed for evaluating a model, characterized as being a computer executable device and circuit simulator. The method includes accepting measured parameters of devices, which devices are essentially identical with, or are actually from, a simulated circuit instance. The model is executed with adjusted input parameters to generate simulated values for properties of the circuit instance. These simulated values are compared with measured values of the same properties. The goodness of the model is determined based on the degree of direct, or statistical, agreement between the simulated and measured values. | 07-14-2011 |
20110219344 | Spatial Correlation-Based Estimation of Yield of Integrated Circuits - Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of failure of a VLSI query design includes the following steps. A Voronoi diagram is built comprising a set of shapes that represent the design. The Voronoi diagram is converted into a rectangular grid comprising 2 | 09-08-2011 |
20110289472 | LAYOUT QUALITY EVALUATION - A method for quantifying and improving layout quality of an IC is disclosed. The method includes receiving a drawn layout and placing essentially one dimensional measurement markers (chords) at various location in the drawn layout. This placement is done in such manner that contours of shapes in the drawn layout intersect a chord in at least two places. The length of the chord is defined as its portion delimited by the intersections, and a measurement of the chord is defined as obtaining its length. The drawn layout is subjected, with the exception of the chords, to a patterning simulation at a selected processing point. Following the simulation the chords are measured and the obtained lengths associated with the drawn layout and the processing point. The patterning simulation may be carried out at a variety processing points and the chord lengths following each simulation are associated with the respective processing point. The sets of lengths obtained at the various processing points are used to quantitatively evaluate the layout quality, to improve the layout quality and tune the processing window. | 11-24-2011 |
20110307430 | Pareto Sampling Using Simplicial Refinement by Derivative Pursuit - A method of optimizing a plurality of objectives includes the steps of initializing a set of simplices; selecting a simplex from the set of simplices; computing one or more weights based at least in part on the selected simplex; and generating a point on a tradeoff surface by utilizing the one or more weights in a weighted-sum optimization. | 12-15-2011 |
20120065765 | DETECTING DOSE AND FOCUS VARIATIONS DURING PHOTOLITHOGRAPHY - A method, system, and computer usable program product for detecting dose and focus variations during photolithography are provided in the illustrative embodiments. A test shape is formed on a wafer, the wafer being used to manufacture integrated circuits, the test shape being formed using a dose value and a focus value that are predetermined for the manufacturing. A capacitance of the test shape is measured. The capacitance is resolved to a second dosing value and a second focus value using an extraction model. A difference between the dosing value and the second dosing value is computed. A recommendation is made for dosing adjustment in the manufacturing based on the difference. | 03-15-2012 |
20120311510 | Spatial Correlation-Based Estimation of Yield of Integrated Circuits - A method for estimating yield of a wafer having a plurality of chips printed thereon is provided which includes the following steps. The chip design is divided into a plurality of rectangular cells. A process window is determined for each of the cells. The focus and dose values on the wafer are measured and used to determine a Gaussian random component of the focus and dose values. The focus and dose values on the wafer are represented as a sum of a systematic component of the focus and dose values and the Gaussian random component. Wafer yield is estimated based on a number of the chips for which at each point (x, y) the focus and dose values, as represented as the sum of the systematic component of the focus and dose values and the Gaussian random component, belong to a corresponding one of the process windows. | 12-06-2012 |
20120330883 | PARETO SAMPLING USING SIMPLICIAL REFINEMENT BY DERIVATIVE PURSUIT - A method of optimizing a plurality of objectives includes the steps of initializing a set of simplices; selecting a simplex from the set of simplices; computing one or more weights based at least in part on the selected simplex; and generating a point on a tradeoff surface by utilizing the one or more weights in a weighted-sum optimization. | 12-27-2012 |
20130226536 | DYNAMICALLY DETERMINING NUMBER OF SIMULATIONS REQUIRED FOR CHARACTERIZING INTRA-CIRCUIT INCONGRUENT VARIATIONS - A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement. | 08-29-2013 |
20130320340 | CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS - A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed. | 12-05-2013 |
20140173535 | ANALYSIS OF CHIP-MEAN VARIATION AND INDEPENDENT INTRA-DIE VARIATION FOR CHIP YIELD DETERMINATION - Systems and methods for determining a chip yield are disclosed. One method includes obtaining a first probability distribution function modeling variations within a chip and a second probability distribution function modeling variations between dies. Further, a discontinuous first level integration is performed with the first probability distribution function and a continuous second level integration is performed by a hardware processor based on the second probability function to determine the chip yield. | 06-19-2014 |
20140173547 | ANALYSIS OF CHIP-MEAN VARIATION AND INDEPENDENT INTRA-DIE VARIATION FOR CHIP YIELD DETERMINATION - Systems and methods for determining a chip yield are disclosed. One system includes a first level integration solver and a second level integration solver. The first level integration solver is configured to obtain a first probability distribution function modeling variations within a chip and to perform a discontinuous first level integration with the first probability distribution function. In addition, the second level integration solver is implemented by a hardware processor and is configured to perform a continuous second level integration based on a second probability distribution function modeling variations between dies to determine the chip yield. | 06-19-2014 |