Patent application number | Description | Published |
20120021712 | Compact low-power receiver including transimpedance amplifier, digitally controlled interface circuit, and low pass filter - According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced. | 01-26-2012 |
20120046004 | High performance transmitter preamplification chain with calibration feedback - According to one embodiment, an improved preamplification chain for implementation in a transmitter comprises a frequency conversion stage for up-converting a baseband signal to a transmit signal, a variable gain control power amplifier driver for preamplifying the transmit signal, and a differential feedback calibration stage receiving first and second differential outputs of a current steering unit of the power amplifier driver and providing calibration feedback to a baseband signal generator of the transmitter. In one embodiment, the frequency conversion stage includes an adjustable low-pass filter for filtering the baseband signal, a passive mixer for up-converting the baseband signal to the transmit signal, and a clock conversion unit configured to convert a fifty percent (50%) duty cycle clock input to a twenty-five percent (25%) duty cycle clock output for driving the passive mixer. | 02-23-2012 |
20120326754 | High Performance Pre-Mixer Buffer in Wireless Communications Systems - According to one embodiment, a high performance buffer for use in a communications system includes first and second differential blocks. Each of the first and second differential blocks comprise one or more driving transistors for generating a driving current for a load of the high performance buffer, and a feedback path for adjusting the operation of the one or more driving transistors. The feedback path includes a feedback transistor for receiving a common mode bias voltage, wherein the common mode bias voltage depends at least in part on a threshold voltage of the feedback transistor. The feedback path includes a programmable resistor and capacitor to reduce out of band loop gain and the noise. The high performance buffer is configured to achieve a high linearity, low output impedance, and low noise, and is suitable for use as a pre-mixer buffer in a wireless communications system. | 12-27-2012 |
20130259163 | Low Power Receiver - According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an s output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TTA) implemented using a current mode to buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced. | 10-03-2013 |
20130259172 | Receiver with Variable Gain Control Transimpedance Amplifier - According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced. | 10-03-2013 |
20140084995 | ENVELOPE DETECTOR WITH ENHANCED LINEAR RANGE - An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of an RF signal input. The detection transistors are configured with a size and for a current such that the transistors are biased in subthreshold regions of operation. The ED core is configured to variably control a bias current through the detection transistors, where the bias current is varied according to a voltage amplitude of the RF signal input to enhance a linear range of the ED while detection transistors continue to operate in subthreshold regions. A linearizer circuit may be configured to control the bias current based on feedback inputs from ED outputs. Several gain-programmable voltage amplifiers, which may include a final specialized class-AB amplifier, precede the ED core, to adapt a transmitter output voltage to an input range of the ED core, which extends the linear range of the ED. | 03-27-2014 |
20140085007 | CLASS-AB RADIO FREQUENCY AMPLIFIER FOR ENVELOPE DETECTOR - An envelope detector (ED) includes a voltage-mode ED core including parallel detection transistors for detecting a voltage envelope of a radio frequency (RF) signal input, the RF signal input including an output of a radio such as a cellular transmitter (TX). The ED further includes multiple voltage amplifiers positioned serially in gain stages between the TX output and the ED core to provide a total linear voltage range of the envelope detector. A final voltage amplifier of the multiple voltage amplifiers drives the ED core and includes a class-AB RF amplifier configured to operate within a full linear voltage range of the ED core. | 03-27-2014 |
20140171005 | LOW-NOISE TIA-TO-ADC INTERFACE WITH A WIDE-RANGE OF PASSIVE GAIN CONTROL - A circuit for a low-noise interface between an amplifier and an analog-to-digital converter (ADC) may comprise a capacitor element having a capacitance of C coupled between a first and second output node of the amplifier. A first resistor R | 06-19-2014 |
20150087245 | RECEIVER FOR CARRIER AGGREGATION - A single hybrid receiver is provided for processing both single carrier and carrier aggregated (CA) communications signals where carriers are split into independent receive paths without any additional external components. The receiver receives all contiguous and non-contiguous intra-band CA and inter-band CA signals allowing for improved rejection and balanced rejection of jamming signals on either side of the two carrier signals. | 03-26-2015 |