Patent application number | Description | Published |
20120290800 | METHOD AND APPARATUS TO REDUCE MEMORY READ LATENCY - A method and apparatus for training read latency of a memory are disclosed. A memory controller includes a command FIFO configured to convey commands to a memory, a data queue coupled to receive data from the memory, and a register configured to provide a value indicative of a number of cycles of a first clock signal after which data is valid. During a startup routine, the memory controller is configured to compare data received by the data queue to a known data pattern after a specified number of cycles of the first clock signal have elapsed. The memory controller is further to configured to decrement the first value and repeat conveying and comparing if the data received matches the data pattern. If the received data does not match the data pattern for any attempted read of the memory, the memory controller is configured to program a second value into the register. | 11-15-2012 |
20140325105 | MEMORY SYSTEM COMPONENTS FOR SPLIT CHANNEL ARCHITECTURE - In one form, a memory module includes a first plurality of memory devices comprising a first rank and having a first group and a second group, and first and second chip select conductors. The first chip select conductor interconnects chip select input terminals of each memory device of the first group, and the second chip select conductor interconnects chip select input terminals of each memory device of the second group. In another form, a system includes a memory controller that performs a first burst access using both first and second portions of a data bus and first and second chip select signals in response to a first access request, and a second burst access using a selected one of the first and second portions of the data bus and a corresponding one of the first and second chip select signals in response to a second access request. | 10-30-2014 |
20150378603 | INTEGRATED CONTROLLER FOR TRAINING MEMORY PHYSICAL LAYER INTERFACE - A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm. | 12-31-2015 |
Patent application number | Description | Published |
20120066445 | DYNAMIC RAM PHY INTERFACE WITH CONFIGURABLE POWER STATES - A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers. | 03-15-2012 |
20120126871 | METHOD AND APPARATUS OF ALTERNATING SERVICE MODES OF AN SOI PROCESS CIRCUIT - A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode. | 05-24-2012 |
20120154011 | METHOD AND APPARATUS FOR PHASE SELECTION ACCELERATION - A method and apparatus for generating a clock that can be switched in phase within a reduced interval of dead time are disclosed. | 06-21-2012 |
20120159271 | MEMORY DIAGNOSTICS SYSTEM AND METHOD WITH HARDWARE-BASED READ/WRITE PATTERNS - A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output. | 06-21-2012 |
20130124806 | DYNAMIC RAM PHY INTERFACE WITH CONFIGURABLE POWER STATES - A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers. | 05-16-2013 |
20150130519 | METHOD AND APPARATUS FOR POWER-UP DETECTION FOR AN ELECTRICAL MONITORING CIRCUIT - A method and apparatus is provided for outputting a reset signal during power-up until two conditions are satisfied. In one embodiment, the method and apparatus includes a voltage detector that provides a first output (“VO1”) when an output voltage of a regulator (“VREG”) exceeds a threshold voltage, thereby satisfying a first condition, a comparator receiving a first input voltage and a second input voltage, the comparator providing a second output (“VO2”) when the first input voltage exceeds the second input voltage, thereby satisfying a second condition, and a release circuit that outputs the reset signal unless the voltage detector provides VO1 while the comparator provides VO2. | 05-14-2015 |
Patent application number | Description | Published |
20100175575 | MULTI-RANGE SHOTSHELLS WITH MULTIMODAL PATTERNING PROPERTIES AND METHODS FOR PRODUCING THE SAME - Shotshells are provided which are loaded with at least two different shot charges, at least one of said charges being comprised of shot pellets with short-range shape(s) and at least another of said charges being comprised of shot pellets with long-range shape(s). Said shotshells are thereby capable of producing shotgun patterns that are suitable for both short-range and long-range shooting. | 07-15-2010 |
20110203477 | FIREARM PROJECTILES AND CARTRIDGES AND METHODS OF MANUFACTURING THE SAME - Firearm projectiles and methods of manufacturing firearm projectiles from a supply of clad wire. In some embodiments, the clad wire is manufactured as electrical wire, such as copper-clad steel wire. Bullets and shot, as well as methods of forming bullets and shot, from clad wire are disclosed. | 08-25-2011 |
20140318403 | CORROSION-INHIBITED PROJECTILES, AND SHOT SHELLS INCLUDING THE SAME - Corrosion-inhibited copper-containing projectiles and shot shells including the same. The projectiles include a core that is formed from a core material, and an outer coating that is formed from a coating material. The core material includes copper, and optionally may include at least 50 wt % copper. In some embodiments, the outer coating maintains a corrosion rate of copper within the core material below 0.00075 mmpy. The shot shells include a shot charge that includes a plurality of the projectiles. | 10-30-2014 |
20150107479 | FIREARM PROJECTILES AND CARTRIDGES AND METHODS OF MANUFACTURING THE SAME - Firearm projectiles and methods of manufacturing firearm projectiles from a supply of clad wire. In some embodiments, the clad wire is manufactured as electrical wire, such as copper-clad steel wire. Bullets and shot, as well as methods of forming bullets and shot, from clad wire are disclosed. | 04-23-2015 |
20150268019 | BALLISTIC ZINC ALLOYS, FIREARM PROJECTILES, AND FIREARM AMMUNITION CONTAINING THE SAME - Firearm cartridges, firearm projectiles, and/or projectile components formed at least in part from a disclosed ballistic zinc alloy. These ballistic zinc alloys overcome shortcomings of other lead substitutes for firearm projectiles, including Zamak alloys and other conventional zinc alloys. In some embodiments, and as compared to a firearm projectile formed from a conventional zinc alloy, a ballistic zinc alloy firearm projectile has at least one of an increased ductility, an increased frangibility, and/or a decreased tendency to smear or gall within a rifled firearm barrel. In some embodiments, the ballistic zinc alloy is a zinc-aluminum alloy that includes additional alloy components that collectively enhance the properties of the ballistic zinc alloy for use in firearm projectiles. | 09-24-2015 |
Patent application number | Description | Published |
20130291571 | METHOD FOR REDUCING TRANSIENT DEFROST NOISE ON AN OUTDOOR SPLIT SYSTEM HEAT PUMP - A method for reducing perceived defrost noise in a heat pump is provided. The method may include energizing a fan configured to urge a heat transfer medium across a heat exchanger, and initiating a defrost cycle to warm the heat exchanger. Initiating the defrost cycle may include de-energizing a compressor fluidly coupled to the heat exchanger, and delaying for a first delay period with the fan energized and the compressor de-energized. Initiating the defrost cycle may also include energizing a reversing valve after the first delay period, to reverse a flow of a refrigerant flow between the compressor and the heat exchanger, and delaying for a second delay period with the fan energized, the compressor de-energized, and the reversing valve energized. Initiating the defrost cycle may also include de-energizing the fan. The method may also include defrosting the heat pump during the defrost cycle, and terminating the defrost cycle. | 11-07-2013 |
20140332189 | FAN COIL UNIT - A fan coil unit is provided including a cabinet formed from a plurality of panels. A fan assembly is configured to circulate air through the cabinet. A heat exchanger assembly is positioned within the cabinet. The heat exchanger assembly includes at least one heat exchanger coil arranged in a heat transfer relationship with the air circulating through the cabinet. An inner surface of at least one of the plurality of panels is partially lined with an elastomeric foam insulation so that the air circulating through the cabinet does not contact the portion of the at least one panel lined with the elastomeric foam insulation. | 11-13-2014 |
20150034290 | AIR HANDLER WITH A LEAK FREE CONTROLS ENCLOSURE - An air handler configured with a second enclosure disposed within the first enclosure to create a continuous airflow passageway, wherein access to the second enclosure does not interrupt the continuous airflow passageway. | 02-05-2015 |
20150338109 | AUXILIARY HEATING ASSEMBLY FOR USE WITH RESIDENTIAL AIR HANDLERS - An auxiliary heating assembly for use with a residential air handler including a fan assembly, the auxiliary heating assembly includes a heating apparatus arranged in a geometric shape, wherein the heating apparatus includes an opening, the opening substantially position in a center of the geometric shape. | 11-26-2015 |