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Amichai
Amichai Givant, Neve Afek IL
| Patent application number | Description | Published |
|---|---|---|
| 20110057241 | FORMING SILICON TRENCH ISOLATION (STI) IN SEMICONDUCTOR DEVICES SELF-ALIGNED TO DIFFUSION - Silicon trench isolation (STI) is formed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The STI may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outside of the corresponding bitlines. The bitline contacts may have sufficient overlap of the bitlines to ensure full coverage by the bitlines. Bitline oxides formed over buried bitlines may be used to self-align trenches of the STI to the bitlines. The STI trenches may be lined with a CMOS spacer, salicide blocking layer and/or a contact etch stop layer. STI may be formed after Poly-2 etch or after word line salicidation. The memory cells may be NVM devices such as NROM, SONOS, SANOS, MANOS, TANOS or Floating Gate (FG) devices. | 03-10-2011 |
Amichai Givant, Rosh-Ha'Ayin IL
| Patent application number | Description | Published |
|---|---|---|
| 20110134713 | Methods circuits devices and systems for operating an array of non-volatile memory cells - Disclosed are methods, circuits, devices and systems for operating one or more non-volatile memory (NVM) cells within an array of NVM cells. According to embodiments, there may be provided a nonvolatile memory (NVM) device comprising an array of NVM data cells including one or more border/periphery data cells and one or more non-periphery cells. Array control circuitry may be adapted to gauge a state of the one or more periphery data cells differently than non-periphery data cells. | 06-09-2011 |
Amichai Nitsan, Rehovot IL
| Patent application number | Description | Published |
|---|---|---|
| 20120096185 | METHODS, SYSTEMS, AND APPARATUS FOR PROCESSING MESSAGING DATA SETS USING STRUCTURED DATA SETS - In one embodiment, a plurality of data conversion modules are bound to a processing engine and a first messaging data set is provided to a conversion module from the plurality of conversion modules. The messaging data set conforms to a messaging format. A structured data set based on a first data portion and a second data portion of the first messaging data set are received and value different from the value of the first data portion is stored within a first element of the structured data set. The value of the second data portion is stored within a second data element of the structured data set. A second messaging data set is then generated based on the structured data set. | 04-19-2012 |
Amichai Sanderovich, Haifa IL
| Patent application number | Description | Published |
|---|---|---|
| 20100199143 | TECHNIQUES FOR ENABLING SIMPLIFIED LDPC ENCODING AND DECODING - A method for low density parity check (LDPC) encoding comprises concatenating a predetermined number of zero bits to a scrambled input data word to generate a concatenated binary sequence; computing parity bits to be added to the concatenated binary sequence, wherein the computing is performed using an LDPC encoder; producing an encoded codeword that consists of the concatenated binary sequence and the parity bits; and replacing the predetermined number of zero bits in the encoded codeword with a scrambled binary sequence, thereby discarding the zero bits. | 08-05-2010 |