Patent application number | Description | Published |
20090248983 | TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS - A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device. | 10-01-2009 |
20100081406 | Dynamic squelch detection power control - In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed. | 04-01-2010 |
20100235320 | ENSURING COHERENCE BETWEEN GRAPHICS AND DISPLAY DOMAINS - A platform may comprise a core coherency domain, graphics coherency domain and a non-coherent domain. A graphics acceleration unit (GAU) of the graphics coherency domain may generate data units from an application and the data units may comprise display data units. The GAU may annotate the display data units with an annotation value before flushing the display data units to an on-die cache. The GAU may identify modified display data units among the display data units stored in the on-die cache and issue flush commands to cause flushing of the modified display data units from the on-die cache to a main memory. The display engine of the non-coherent domain may use the modified display data units stored in the main memory to render a display on a display device. | 09-16-2010 |
20120200585 | TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS - A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device. | 08-09-2012 |
20130007751 | METHOD AND SYSTEM FOR SAFE ENQUEUING OF EVENTS - A method and system to facilitate a user level application executing in a first processing unit to enqueue work or task(s) safely for a second processing unit without performing any ring transition. For example, in one embodiment of the invention, the first processing unit executes one or more user level applications, where each user level application has a task to be offloaded to a second processing unit. The first processing unit signals the second processing unit to handle the task from each user level application without performing any ring transition in one embodiment of the invention. | 01-03-2013 |
20130117509 | TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS - A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device. | 05-09-2013 |
20130159820 | DYNAMIC ERROR HANDLING USING PARITY AND REDUNDANT ROWS - Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space. | 06-20-2013 |
20130207987 | TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS - A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device. | 08-15-2013 |
20140025908 | FAST MECHANISM FOR ACCESSING 2n.+-.1 INTERLEAVED MEMORY SYSTEM - A mechanism implemented by a controller enables efficient access to an interleaved memory system that includes M modules, M being (2 | 01-23-2014 |
20140068626 | Direct Ring 3 Submission of Processing Jobs to Adjunct Processors - Transitions to ring 0, each time an application wants to use an adjunct processor, are avoided, saving central processor operating cycles and improving efficiency. Instead, initially each application is registered and setup to use adjunct processor resources in ring 3. | 03-06-2014 |
20140125679 | Dynamically Rebalancing Graphics Processor Resources - According to some embodiments, performance bottlenecks that arise in particular resources within a graphic processor unit may be alleviated by dynamically rebalancing workloads among the resources, with the goal of removing the current performance bottleneck, while at the same time maintaining power dissipation within a currently allocated power budget. In some embodiments this may be achieved by defining a separate clock domain for each of the plurality of graphics processor resources whose performance may then be rebalanced. | 05-08-2014 |
20140136797 | TECHNIQUE TO SHARE INFORMATION AMONG DIFFERENT CACHE COHERENCY DOMAINS - A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device. | 05-15-2014 |
20140267323 | MEMORY MAPPING FOR A GRAPHICS PROCESSING UNIT - An electronic device is described herein. The electronic device may include a page walker module to receive a page request of a graphics processing unit (GPU). The page walker module may detect a page fault associated with the page request. The electronic device may include a controller, at least partially comprising hardware logic. The controller is to monitor execution of the page request having the page fault. The controller determines whether to suspend execution of a work item at the GPU associated with the page request having the page fault, or to continue execution of the work item based on factors associated with the page request. | 09-18-2014 |
20140306949 | SCALABLE GEOMETRY PROCESSING WITHIN A CHECKERBOARD MULTI-GPU CONFIGURATION - Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores. | 10-16-2014 |
20140359220 | Scatter/Gather Capable System Coherent Cache - In accordance with some embodiments, a scatter/gather memory approach may be enabled that is exposed or backed by system memory and uses conventional tags and addresses. Thus, such a technique may be more amenable to conventional software developers and their conventional techniques. | 12-04-2014 |
20140375661 | PAGE MANAGEMENT APPROACH TO FULLY UTILIZE HARDWARE CACHES FOR TILED RENDERING - Systems and methods may provide for identifying a tile associated with an image and ordering an entirety of the tile into a linear stream of pages associated with a frame buffer. Additionally, the linear stream of pages may be allocated to a cache. In one example, the linear stream of pages is allocated to the cache in accordance with a fixed set selection policy of the cache. | 12-25-2014 |
20150035840 | USING GROUP PAGE FAULT DESCRIPTORS TO HANDLE CONTEXT SWITCHES AND PROCESS TERMINATIONS IN GRAPHICS PROCESSORS - Methods and systems may provide for detecting an end of execution of a process on a graphics processor and providing a group page fault descriptor to a page miss handler of an operating system (OS) in response to the end of execution of the process, wherein the group page fault descriptor may indicate to the page miss handler that no further page fault requests will be generated by the graphics processor until one or more outstanding page fault requests are satisfied. Additionally, a response to the group page fault descriptor may be received from the page miss handler. In one example, a process identifier is incorporated into the group page fault descriptor, wherein the process identifier is shared by the group page fault descriptor and the one or more outstanding page fault requests. | 02-05-2015 |