Patent application number | Description | Published |
20080201511 | Device Identification Coding of Inter-Integrated Circuit Slave Devices - Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate identification of inter-integrated circuit slave devices using device identification coding. The communications system includes a slave device having a device identification code identifying one or more parameters. Communications circuitry in the slave device is configured to communicate with a master device on the I2C serial data transfer bus using the communications protocol. In response to a transmission of a device identification address from the master device, the slave device is configured to transmit an ACKNOWLEDGE, and in response to a transmission of a slave device address and the device identification address from the master device, the slave device is configured to transmit the device identification code from the slave device to the master. | 08-21-2008 |
20080215779 | Slave Device with Latched Request for Service - Consistent with one example embodiment, communications systems ( | 09-04-2008 |
20080215780 | Simultaneous Control Of Multiple I/O Banks In An 12C Slave Device - Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device registers. The communications system includes a slave device having two or more registers, each register having two or more bits, each register configured to load data therein received in accordance with the communications protocol over the data transfer bus in a first configuration, and to load a single logic value into the plurality of bits in a second configuration. A programmable configuration register is configured to be programmed, in accordance with the communications protocol over the data transfer bus, to select two or more of the registers for loading of the single logic value into the two or more of bits of the selected registers in the second configuration. | 09-04-2008 |
20080252407 | Multi-Layer Inductive Element for Integrated Circuit - According to one example embodiment, an inductive element is used for power-conversion applications. The inductive element includes a substrate ( | 10-16-2008 |
20090066381 | EDGE RATE CONTROL FOR I2C BUS APPLICATIONS | 03-12-2009 |
20090096392 | PULSE WIDTH MODULATION BASED LED DIMMER CONTROL - Methods and apparatus for implementing and operating pulse width modulation based LED dimmer controllers are described. A synchronization protocol is used to allow control information for the dimmer operations to be transferred to the PWM dimmer control clock domain from an external clock domain, such that visual artifacts are prevented when the control information is updated. Control information may be transferred to the LED dimmer controller via an I2C serial bus, and the synchronization protocol waits for an I2C STOP condition before updating control information across clock domain boundaries. The leading and trailing edges of an asserted group dimmer control signal are generated such that the active portion of the group dimmer control signal overlaps the active portion of individual LED pulse width modulated control signals. In this way, the pulse width modulation of the individual LED control signals is not cut off, or reduced in width by the group dimmer signal. | 04-16-2009 |
20100205326 | PROGRAMMING PARALLEL I2C SLAVE DEVICES FROM A SINGLE I2C DATA STREAM - Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programming of parallel slave devices concurrently using an I | 08-12-2010 |
20100217903 | SIMULTANEOUS CONTROL OF MULTIPLE I/O BANKS IN AN I2C SLAVE DEVICE - Consistent with one example embodiment, communications systems ( | 08-26-2010 |
20100237919 | METHOD AND SYSTEM FOR A SIGNAL DRIVER USING CAPACITIVE FEEDBACK - Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor ( | 09-23-2010 |
20100264970 | EDGE RATE CONTROL FOR I2C BUS APPLICATIONS - Consistent with an example embodiment, an edge-rate control circuit arrangement ( | 10-21-2010 |
20140055186 | ASYMMETRIC PROPAGATION DELAYS IN LEVEL SHIFTERS AND RELATED CIRCUITS - Aspects of the present disclosure are directed towards apparatus useful for processing communications between different signaling voltage levels. Different signaling voltage levels are accomplished by creating true and complement signals from at least one input signal, each of which are subject to different delays, and level shifting the true and complement signals to a new signaling voltage level. The true or complement signal subject to a smaller timing delay is selected, and used to provide an output signal. | 02-27-2014 |
20140347111 | SLEW RATE CONTROL FOR MULTIPLE VOLTAGE DOMAINS - A reference output device includes a low side selector configured to select a first voltage level as an output signal. The output signal is a reference voltage. The reference output device also includes a high side selector configured to select a second voltage level as the output signal. The reference output device also includes a slew rate control configured to switch the output signal between the first voltage level and the second voltage level at a constant slew rate. | 11-27-2014 |