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Allarey
Jose Allarey, Davis, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090199024 | METHOD, APPARATUS AND SYSTEM TO DYNAMICALLY CHOOSE AN AOPTIMUM POWER STATE - Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described. | 08-06-2009 |
| 20100083021 | Voltage stabilization for clock signal frequency locking - A processor, system, and method are disclosed. In an embodiment, the processor includes a first site and a second site. There is a link to transmit a voltage stabilization signal from the second site to the first site. In the first site voltage correction logic can dynamically modify a voltage supplied to the first site and second site. In the second site there is logic to assert the voltage stabilization signal. After asserting the voltage stabilization signal, the second site is granted at least a window of time in which the supplied voltage to the second site does not change. | 04-01-2010 |
Jose Allarey, Rancho Cordova, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090024799 | Technique for preserving cached information during a low power mode - A technique to retain cached information during a low power mode, according to at least one embodiment. In one embodiment, information stored in a processor's local cache is saved to a shared cache before the processor is placed into a low power mode, such that other processors may access information from the shared cache instead of causing the low power mode processor to return from the low power mode to service an access to its local cache. | 01-22-2009 |
Jose P Allarey, Davis, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080244294 | Dynamic power reduction - Some embodiments of the invention include systems, apparatuses, and methods for dynamically reducing requested supply voltage based on idle functional blocks. | 10-02-2008 |
| 20090132844 | Method, Apparatus, and System for optimizing Frequency and Performance in a Multi-Die Microprocessor - With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status. | 05-21-2009 |
| 20110138388 | METHODS AND APPARATUSES TO IMPROVE TURBO PERFORMANCE FOR EVENTS HANDLING - Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses. | 06-09-2011 |
| 20110154081 | DYNAMIC POWER REDUCTION - Some embodiments of the invention include systems, apparatuses, and methods for dynamically reducing requested supply voltage based on idle functional blocks. | 06-23-2011 |
Mary Jean Allarey, Davis, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110138388 | METHODS AND APPARATUSES TO IMPROVE TURBO PERFORMANCE FOR EVENTS HANDLING - Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses. | 06-09-2011 |