Patent application number | Description | Published |
20110093236 | PROCESSING POSITION-RELATED INPUT DATA FROM A ROTATIONAL MACHINE WHOSE ANGULAR SPEED IS VARIABLE - A data processor and method for processing position-related input data from a rotational machine whose angular speed is variable and providing output data at an output data rate. The processor comprises a time-based over-sampler for over-sampling the input data at an over-sampling rate greater than the output data rate, and a down-sampler for extracting samples of over-sampled data from the over-sampler at the output data rate so as to provide the output data. The down-sampler is responsive to an angular timing signal related to an angular position of the machine for selecting the samples of over-sampled data to extract based on the angular position. Application to a rotational machine whose angular speed is variable, in particular to an internal combustion engine to control engine operating parameters as a function of cylinder pressure. | 04-21-2011 |
20110258462 | METHOD, SYSTEM AND INTEGRATED CIRCUIT FOR ENABLING ACCESS TO A MEMORY ELEMENT - A system comprises signal processing logic that is operably coupled to at least one memory element and is arranged to enable access to the at least one memory element. The signal processing logic is arranged to receive a security key, generate a system key using the received security key and a system specific seed, perform a comparison of the generated system key to a reference key stored in an area of memory of the at least one memory element. The signal processing logic is also arranged to configure a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory. | 10-20-2011 |
20120124336 | SIGNAL PROCESSING SYSTEM AND INTEGRATED CIRCUIT COMPRISING A PREFETCH MODULE AND METHOD THEREFOR - A signal processing system comprising at least one master device at least one memory element and prefetch module arranged to perform prefetching from at least one memory element upon a memory access request to the at least one memory element from the at least one master device. Upon receiving a memory access request from the at least one master device, the prefetch module is arranged to configure the enabling of prefetching of at least one of instruction information and data information in relation to that memory access request based at least partly on an address to which the memory access request relates. | 05-17-2012 |
20120131241 | SIGNAL PROCESSING SYSTEM, INTEGRATED CIRCUIT COMPRISING BUFFER CONTROL LOGIC AND METHOD THEREFOR - A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorise the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritise respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered. | 05-24-2012 |
20130227256 | METHOD FOR SETTING BREAKPOINTS, AND AN INTEGRATED CIRCUIT AND DEBUG TOOL THEREFOR - A method for setting one or more breakpoints within executable program code of an embedded device is described. The method comprises copying at least one area of non-volatile memory (NVM) of the embedded device, comprising at least one instruction at which a breakpoint is to be set, into at least one area of overlay memory replacing within the overlay memory the at least one instruction at which a breakpoint is to be set with a breakpoint operation code, and enabling a mapping of the at least one area of NVM, comprising the at least one instruction at which a breakpoint is to be set, to the at least one area of overlay memory during execution of the program code within the embedded device. | 08-29-2013 |
20130229737 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR DETECTING AN EXCESSIVE VOLTAGE STATE - An integrated circuit device comprising at least one analogue to digital converter. The at least one ADC comprises at least one input operably coupled to at least one external contact of the integrated circuit device. The integrated circuit device further comprises detection circuitry comprising at least one detection module. The at least one detection module being arranged to receive at a first input thereof an indication of a voltage level at the at least one input of the at least one ADC, compare the received indication to a threshold value, and if the received indication exceeds the threshold value, output an indication that an excessive voltage state at the at least one input of the at least one ADC has been detected. | 09-05-2013 |
20130232330 | METHOD FOR ENABLING CALIBRATION DURING START-UP OF A MICRO CONTROLLER UNIT AND INTEGRATED CIRCUIT THEREFOR - A method for enabling calibration during start-up of a micro controller unit device is provided. The method comprises, within the MCU device, reading overlay initialisation data from at least one memory element within an external support device operably coupled to the MCU device, and configuring memory mapping functionality of the MCU device to overlay data stored within at least a part of device memory of the MCU device with calibration data stored within the at least one memory element of the external support device in accordance with the overlay initialisation data. | 09-05-2013 |
20130246695 | INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM AND METHOD FOR PREFETCHING LINES OF DATA THEREFOR - An integrated circuit device comprising at least one prefetching module for prefetching lines of data from at least one memory element. The prefetching module is configured to determine a position of a requested block of data within a respective line of data of the at least one memory element, determine a number of subsequent lines of data to prefetch, based at least partly on the determined position of the requested block of data within the respective line of data of the at least one memory element, and cause the prefetching of n successive lines of data from the at least one memory element. | 09-19-2013 |