Patent application number | Description | Published |
20090039952 | System and Method for Auto-Power Gating Synthesis for Active Leakage Reduction - A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software. | 02-12-2009 |
20090262588 | POWER SAVINGS WITH A LEVEL-SHIFTING BOUNDARY ISOLATION FLIP-FLOP (LSIFF) AND A CLOCK CONTROLLED DATA RETENTION SCHEME - An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input. | 10-22-2009 |
20090267638 | Apparatus, System and Method of Power State Control - An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch. | 10-29-2009 |
20100103760 | Memory Power Management Systems and Methods - Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array. | 04-29-2010 |
20100253387 | SYSTEM AND METHOD FOR AUTO-POWER GATING SYNTHESIS FOR ACTIVE LEAKAGE REDUCTION - A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software. | 10-07-2010 |
20100287517 | Statistical Static Timing Analysis in Non-Linear Regions - A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths. | 11-11-2010 |
20110216619 | MEMORY POWER MANAGEMENT SYSTEMS AND METHODS - Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array. | 09-08-2011 |
20120060138 | Method and System for Adaptive Physical Design - A method is provided that includes performing a free placement of a system design comprising a plurality of power domains, wherein the power domains are not constrained to physical regions, assigning a physical region to each of the power domains based on the free placement of cells in the power domains, performing a soft cluster placement of the system design with each power domain and corresponding physical region defined as a soft cluster, refining at least one physical region based on the soft cluster placement, redefining cells in at least one power domain based on the soft cluster placement of the cells and the corresponding physical region, and performing a hard cluster placement of the system design with each power domain and corresponding physical region defined as a hard cluster to generate final power domains. | 03-08-2012 |
20130154723 | PERFORMANCE, THERMAL AND POWER MANAGEMENT SYSTEM ASSOCIATED WITH AN INTEGRATED CIRCUIT AND RELATED METHOD - The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC. | 06-20-2013 |
20130222069 | Systems and Methods of Low Power Clocking for Sleep Mode Radios - Systems and methods of low power clocking of sleep mode radios are disclosed herein. In an example embodiment, a crystal oscillator is purposefully mistuned to achieve lower power consumption, and then synchronized using a high frequency crystal oscillator. In an alternative embodiment, the input offset voltages of the comparator in an RC oscillator are cancelled, which allows low power operation and high accuracy performance when tuned to the high frequency crystal. A lower power comparator may be used with higher input offset voltages but still achieve higher accuracy. The RC circuit is switched back and forth on opposite phases of the output, cancelling the offset voltage on the inputs of the comparator. | 08-29-2013 |
20140095919 | CLOCK CONTROL METHOD FOR PERFORMANCE THERMAL AND POWER MANAGEMENT SYSTEM - A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period. | 04-03-2014 |
20150022254 | PERFORMANCE, THERMAL AND POWER MANAGEMENT SYSTEM ASSOCIATED WITH AN INTEGRATED CIRCUIT AND RELATED METHOD - The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC. | 01-22-2015 |
20150022260 | PERFORMANCE, THERMAL AND POWER MANAGEMENT SYSTEM ASSOCIATED WITH AN INTEGRATED CIRCUIT AND RELATED METHOD - The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC may be set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC. | 01-22-2015 |
20150025829 | PERFORMANCE, THERMAL AND POWER MANAGEMENT SYSTEM ASSOCIATED WITH AN INTEGRATED CIRCUIT AND RELATED METHOD - The performance, thermal and power management system is configured to perform DVFS calibration, temperature compensation adjustment, aging calibration, and DC offset calibration in an IC. The initial voltage supplied to the IC maybe set to an initial value which takes chip-to-chip process variations into account and then dynamically adjusted according to temperature variations, DC offset and/or aging effects. Therefore, the performance, thermal and power management system may achieve optimized thermal and power performance of the IC. | 01-22-2015 |