Aliaksei

Aliaksei Chapyzhenka, Saint Petersburg RU

Patent application number	Description	Published
20080292025	Low Density Parity Check (Ldpc) Code Decoder - A message-passing decoder for low-density parity-check codes (LDPC) is provided using a multi-value threshold scheme which is updated throughout the decoding iterations. In an embodiment the check node processing is implemented using the min-sum principle whereby for each corresponding row of the parity check matrix a first and a second minimum value among bit reliability values is determined. Each row of the decoder comprises one or more associative processing elements controlled by a row control element to determine the two minimum values. Each column comprises one or more associative processing elements, an input processing element, and a column control element to determine hard decision bits. The usage of processing elements to construct a decoder may reduce the gate count and decrease the interconnects used to couple the elements.	11-27-2008

Patent application number	Description	Published
20080253278	Techniques to Compress Modulation Patterns for Adaptive Bitloading - An embodiment of the present invention provides a method, comprising using a predetermined limited set of modulation patterns to perform adaptive bit loading (ABL) to compress the modulation patterns in wireless communications.	10-16-2008

Patent application number	Description	Published
20100333203	METHODS FOR DETECTING MALICIOUS PROGRAMS USING A MULTILAYERED HEURISTICS APPROACH - Three heuristic layers are used to determine whether suspicious code received at a port of a data processing device is malware. First, static analysis is applied to the suspicious code. If the suspicious code passes the static analysis, dissembling analysis is applied to the suspicious code. Preferably, if the suspicious code passes the dissembling analysis, dynamic analysis is applied to the suspicious code.	12-30-2010