Patent application number | Description | Published |
20080263120 | METHOD AND SYSTEM FOR OPTIMIZING FLOATING POINT CONVERSION BETWEEN DIFFERENT BASES - A method of streamlining floating-point conversions includes determining a source coefficient and a source exponent of an input value represented by a floating-point number in a source base; estimating an approximated target exponent (ATE) using the source coefficient and the source exponent, in the event the source coefficient has a non-zero value; determining whether the ATE exceeds a maximum exponent so as to result an overflow, and outputting a predefined overflow value in the event of an overflow; determining whether the ATE exceeds a minimum exponent so as to result an underflow, and outputting a predefined underflow value in the event of an underflow; and in the event the ATE does not result in either an overflow or underflow, converting the input value to an output value represented by a converted coefficient, a converted base and the exponent of the output value. | 10-23-2008 |
20080263121 | METHOD AND SYSTEM FOR OPTIMIZING FLOATING POINT CONVERSION BETWEEN DIFFERENT BASES - A method of performing floating-point conversions in a digital computing system includes determining a source coefficient, c | 10-23-2008 |
20090222696 | SYSTEM AND METHOD FOR DETECTING NON-REPRODUCIBLE PSEUDO-RANDOM TEST CASES - A method for monitoring a test case generator system by detecting non-reproducible pseudo-random test cases, comprising: building a first pseudo-random test case having a first sequence of seeds comprising a first starting seed and a first ending seed through the test case generator system; reproducing the first sequence of seeds of the first pseudo-random test case by building a second pseudo-random test case having a second sequence of seeds comprising a second starting seed and a second ending seed through the test case generator system when the test case generator system is operating in a reproduction mode, the first starting seed being used as the second starting seed of the second sequence of seeds; and comparing the first ending seed in the first sequence of seeds to the second ending seed in the second sequence of seeds. | 09-03-2009 |
20110145308 | SYSTEM TO IMPROVE NUMEREICAL CONVERSIONS AND ASSOCIATED METHODS - A system to improve numerical conversion may include a data processor and a controller configured to convert a floating-point number from the data processor to more than one different floating-point type number. The conversion may enable the selection of the more than one different floating-point type number that satisfies the requirements of an executing application and/or is closest to the original number. | 06-16-2011 |
20120131560 | VIRTUAL MACHINE TESTING - A system for testing a base machine includes the base machine that has a base feature set (BFS) and a testing module. The system also includes a test case generator, configured to: select a prior level of the base machine, the prior level having a legacy architecture; determine a feature set of the legacy architecture based on the BFS; generate a set of test instructions based on the feature set; and provide the set of test instructions to the testing module. | 05-24-2012 |
20130191105 | VIRTUAL SYSTEMS TESTING - According to exemplary embodiments, a computer program product for testing virtual systems includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method comprises randomly selecting commands from a pool of commands, generating by a computer a test sequence from the randomly selected commands and simulating performance of the test sequence for a simulated virtual system that is a model of a virtual system. The method also includes recording simulated results of the simulated performance, performing the test sequence on the virtual system, recording actual results of the test sequence being performed on the virtual system, and determining by a computer if the virtual system is operating properly based on a comparison of the simulated results to the actual results. | 07-25-2013 |
20140081615 | VIRTUAL SYSTEMS TESTING - According to exemplary embodiments, a computer program product for testing virtual systems includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method comprises randomly selecting commands from a pool of commands, generating by a computer a test sequence from the randomly selected commands and simulating performance of the test sequence for a simulated virtual system that is a model of a virtual system. The method also includes recording simulated results of the simulated performance, performing the test sequence on the virtual system, recording actual results of the test sequence being performed on the virtual system, and determining by a computer if the virtual system is operating properly based on a comparison of the simulated results to the actual results. | 03-20-2014 |
20140245074 | TESTING OF RUN-TIME INSTRUMENTATION - A computer program product is provided for performing a method including: generating a test instruction stream of a program that includes a plurality of executable instructions; setting controls for a runtime-instrumentation process; simulating execution of the test instruction stream and sampling of the test instruction stream according to the controls, and storing simulated records associated with the sampling in a predicted collection buffer (PCB); accessing a program buffer of a processor, the program buffer storing records associated with sampling the test instruction stream according to the controls during execution of the test instruction stream by the processor; examining individual records in the program buffer to determine whether the individual records are valid and in proper sequence; and comparing the simulated records of the PCB and the records of the program buffer to validate the program buffer. | 08-28-2014 |
20140250329 | SYSTEM LEVEL ARCHITECTURE VERIFICATION FOR TRANSACTION EXECUTION IN A MULTI-PROCESSING ENVIRONMENT - Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output to one or more output devices. | 09-04-2014 |
20140250330 | SYSTEM LEVEL ARCHITECTURE VERIFICATION OF A TRANSACTIONAL EXECUTION - Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution, testing, by the computing device, the transaction execution in a uni-processing system based on the instruction stream, and outputting, by the computing device, a status of the test to one or more output devices. A determination may be made that an abort occurs in the transaction execution based on the testing. | 09-04-2014 |
20150019846 | SYSTEM LEVEL ARCHITECTURE VERIFICATION FOR TRANSACTION EXECUTION IN A MULTI-PROCESSING ENVIRONMENT - Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output to one or more output devices. | 01-15-2015 |