Patent application number | Description | Published |
20110072326 | SRAM MACRO TEST FLOP - A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit. | 03-24-2011 |
20120218034 | VOLTAGE CALIBRATION METHOD AND APPARATUS - A method and apparatus for power supply calibration to reduce voltage guardbands is disclosed. In one embodiment, an integrated circuit (IC) includes a voltage measurement unit configured to measure an operating voltage during a start-up procedure. The IC further includes a comparator configured to compare the measured operating voltage to a target voltage. The comparator is further configured to cause a change to a supply voltage (upon which the operating voltage is based) if the operating voltage is not within a target voltage range and to repeat the measurement of the operating voltage. If the operating voltage is within the target voltage range, the comparator is configured to inhibit further changes to the operating voltage. | 08-30-2012 |
20130086417 | Systems and Methods for Retiring and Unretiring Cache Lines - The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure. | 04-04-2013 |
20130311814 | CONSTANT FREQUENCY ARCHITECTURAL TIMER IN A DYNAMIC CLOCK DOMAIN - Implementations of the present disclosure involve an apparatus and/or method for providing a constant frequency timer signal for a microprocessor that operates with varying core clock signals. The apparatus and/or method utilizes a code generator, such as a gray code generator, operating on a reference clock signal that allows the constant frequency timer signal to be either faster or slower than the core clock frequency. More particularly, the apparatus and/or method may compute a difference between previous gray code samples and add the calculated difference to a software visible reference clock signal such that constant frequency timer signal may be faster or slower than the core clock signal. Through the use of the apparatus and/or method, a core clock signal may be reduced as needed to provide operational power savings to the microprocessor and the computing system employing the techniques described herein, while maintaining synchronization between the executing programs of the computing system. | 11-21-2013 |
20140032887 | HYBRID HARDWIRED/PROGRAMMABLE RESET SEQUENCE CONTROLLER - A processor having a number of functional units includes a hybrid reset sequence controller that includes a master reset controller that may be configured to hierarchically control a sequence of initialization operations performed on the functional units based upon a value stored within a master control register. In addition, the processor may also include a number of additional controllers, each configured to control initialization operations for a respective functional unit based upon a value stored within an additional respective control register. The master reset controller may control each of the additional reset controllers dependent on the value stored within the master control register | 01-30-2014 |
20140047151 | INTERRUPT PROCESSING UNIT FOR PREVENTING INTERRUPT LOSS - Techniques are disclosed relating to systems that allow sending and receiving of interrupts between processing elements. In various embodiments, a system includes an interrupt processing unit that in turn includes various indicators corresponding to processing elements. In some embodiments, the interrupt processing unit may be configured to receive an interrupt and determine whether a first processing element associated with the interrupt is available to receive interrupts. The system may initiate a corrective action if the first processing element is not available to receive interrupts. In some embodiments, the corrective action may include redirecting the interrupt to a second processing element. In some embodiments, the interrupt processing unit may include a dropped interrupt management register to store information corresponding to the second processing element. In some embodiments, the corrective action may include altering the power state of the first processing element such that it becomes available to receive interrupts. | 02-13-2014 |
20140047284 | COMBO STATIC FLOP WITH FULL TEST - A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master storage node and a multiplexer. The slave latch circuit includes a slave storage node driven by the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from the master latch circuit and a slave driver driven from the slave latch circuit. | 02-13-2014 |
20140052966 | MECHANISM FOR CONSISTENT CORE HANG DETECTION IN A PROCESSOR CORE - Mechanism for consistent core hang detection on a processor with multiple processor cores, each having one or more instruction execution pipelines. Each core may also include a hang detection unit with a counter unit that may generate a count value based on a clock source having a frequency that is independent of a frequency of a processor core clock. The hang detection unit may also include a detector logic unit that may determine whether a given instruction execution pipeline has ceased processing a given instruction based upon a state of the processor core and whether or not the given instruction has completed execution prior to the count value exceeding a predetermined value. | 02-20-2014 |
20140082396 | METHOD AND APPARATUS FOR DISTRIBUTED GENERATION OF MULTIPLE CONFIGURABLE RATIOED CLOCK DOMAINS WITHIN A HIGH SPEED DOMAIN - Implementations of the present disclosure involve an apparatus and/or method for providing one or more clock signals within a processing device. In particular, one or more counter devices may be integrated into a microprocessor design that operates on a system clock signal to provide ratioed synchronous clock signals for use by the microprocessor. Additionally, one or more synchronization pulse signals are also generated from the one or more counter devices to facilitate communication between domains of the microprocessor that may operate on separate clock frequencies. Such synchronization pulse signals may also provide for a virtual clock signal within a clock domain to create a low frequency logic cluster within a high frequency domain of the microprocessor. A synchronous, low frequency reset signal is also disclosed to synchronize the counting devices to the system clock without the need for an additional high frequency signal path in the microprocessor design. | 03-20-2014 |
20140136909 | TESTING OF SRAMS - Systems, methods, and other embodiments associated with at-speed testing of static random access memory (SRAM) are described. In one embodiment, a method includes loading, into a multi-stage pipeline of memory devices, a control pattern for testing a static random access memory (SRAM). The SRAM is tested by generating a test input that is based, at least in part, on the control pattern from the multi-stage pipeline of flip-flops. The test input is provided to the SRAM over a series of clock cycles that are at a core clock speed of the SRAM. | 05-15-2014 |
20140136912 | COMBO DYNAMIC FLOP WITH SCAN - A combo dynamic flop with scan flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a dynamic latch circuit and a static latch circuit. The dynamic latch circuit includes a dynamic latch storage node. The static latch circuit includes a static storage node driven by the dynamic latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the static latch. The output buffer circuit includes a dynamic latch driver driven from the dynamic latch circuit and a static driver driven from the static latch circuit. | 05-15-2014 |
20140143580 | METHOD AND APPARATUS FOR SYNCHRONIZING THE TIME REFERENCE OF A DYNAMICALLY ACTIVATED PROCESSOR TO THE SYSTEM TIME REFERENCE - Implementations of the present disclosure involve an apparatus and/or method for synchronizing at least one newly activated processor with at least one previously running processor. Each processor is configured to generate a heartbeat and operate according to a STICK. When a previously deactivated processor is added, the heartbeat of each active processor is reset and the current STICK is transmitted to the newly activated processor on the next heartbeat. The newly activated processor may then add the heartbeat period to the acquired STICK and begin incrementing the STICK and normal operation after the next heartbeat. | 05-22-2014 |
20140210526 | Rotational Synchronizer Circuit for Metastablity Resolution - A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is configured to select one of its inputs to be coupled to the output. A control circuit is configured to cause the multiplexer to sequentially select outputs of the M+1 latches responsive to N successive clock pulses, and further configured to cause the M+1 latches to sequentially latch data received through the common data input. | 07-31-2014 |
20150039938 | Systems and Methods for Retiring and Unretiring Cache Lines - The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure. | 02-05-2015 |