| Patent application number | Description | Published |
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| 20080270745 | Hardware acceleration of a write-buffering software transactional memory - A method and apparatus for accelerating a software transactional memory (STM) system is described herein. Annotation field are associated with lines of a transactional memory. An annotation field associated with a line of the transaction memory is initialized to a first value upon starting a transaction. In response to encountering a read operation in the transaction, then annotation field is checked. If the annotation field includes a first value, the read is serviced from the line of the transaction memory without having to search an additional write space. A second and third value in the annotation field potentially indicates whether a read operation missed the transactional memory or a tentative value is stored in a write space. Additionally, an additional bit in the annotation field, may be utilized to indicate whether previous read operations have been logged, allowing for subsequent redundant read logging to be reduced. | 10-30-2008 |
| 20090006767 | USING EPHEMERAL STORES FOR FINE-GRAINED CONFLICT DETECTION IN A HARDWARE ACCELERATED STM - A method and apparatus for fine-grained filtering in a hardware accelerated software transactional memory system is herein described. A data object, which may have any arbitrary size, is associated with a filter word. The filter word is in a first default state when no access, such as a read, from the data object has occurred during a pendancy of a transaction. Upon encountering a first access, such as a first read, from the data object, access barrier operations including an ephemeral/private store operation to set the filter word to a second state are performed. Upon a subsequent/redundant access, such as a second read, the access barrier operations are elided to accelerate the subsequent access, based on the filter word being set to the second state to indicate a previous access occurred. | 01-01-2009 |
| 20090077339 | OBJECT BASED CONFLICT DETECTION IN A SOFTWARE TRANSACTIONAL MEMORY - Object-based conflict detection is described in the context of software transactional memory. In one example, a pointer is received for a block of instructions, the block of instructions having allocated objects. The lower bits of the pointer are masked if the pointer is in a small object space to obtain a block header for the block, and a size of the allocated objects is determined using the block header. | 03-19-2009 |
| 20090089520 | Hardware acceleration of strongly atomic software transactional memory - In accordance with some embodiments, software transactional memory may be used for both managed and unmanaged environments. If a cache line is resident in a cache and this is not the first time that the cache line has been read since the last write, then the data may be read directly from the cache line, improving performance. Otherwise, a normal read may be utilized to read the information. Similarly, write performance can be accelerated in some instances to improve performance. | 04-02-2009 |
| 20090172292 | ACCELERATING SOFTWARE LOOKUPS BY USING BUFFERED OR EPHEMERAL STORES - A method and apparatus for accelerating lookups in an address based table is herein described. When an address and value pair is added to an address based table, the value is privately stored in the address to allow for quick and efficient local access to the value. In response to the private store, a cache line holding the value is transitioned to a private state, to ensure the value is not made globally visible. Upon eviction of the privately held cache line, the information is not written-back to ensure locality of the value. In one embodiment, the address based table includes a transactional write buffer to hold addresses, which correspond to tentatively updated values during a transaction. Accesses to the tentative values during the transaction may be accelerated through use of annotation bits and private stores as discussed herein. Upon commit of the transaction, the values are copied to the location to make the updates globally visible. | 07-02-2009 |
| 20090172303 | HYBRID TRANSACTIONS FOR LOW-OVERHEAD SPECULATIVE PARALLELIZATION - A method and apparatus for a hybrid transactional memory system is herein described. A first transaction is executed utilizing a first style of a transactional memory system and a second transaction is executed in parallel utilizing a second style of a transactional memory system. For example, a main thread is executed utilizing an update-in place Software Transactional Memory (STM) system while a parallel thread, such as a helper thread, is executed utilizing a write buffering STM. As a result, a main thread may directly update memory locations, while a helper thread's transactional writes are buffered to ensure they do not invalidate transactional reads of the main thread. Therefore, parallel execution of threads is achieved, while ensuring at least one thread, such as a main thread, does not degrade below an amount of execution cycles it would take to execute the main thread serially. | 07-02-2009 |
| 20090172305 | EFFICIENT NON-TRANSACTIONAL WRITE BARRIERS FOR STRONG ATOMICITY - A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations. | 07-02-2009 |
| 20090172317 | MECHANISMS FOR STRONG ATOMICITY IN A TRANSACTIONAL MEMORY SYSTEM - A method and apparatus for providing efficient strong atomicity is herein described. Optimized strong operations may be inserted at non-transactional read accesses to provide efficient strong atomicity. A global transaction value is copied at a beginning of a non-transational function to a local transaction value; essentially creating a local timestamp of the global transaction value. At a non-transactional memory access within the function, a counter value or version value is compared to the LTV to see if a transaction has started updating memory locations, or specifically the memory location accessed. If memory locations have not been updated by a transaction, execution is accelerated by avoiding a full set of slowpath strong atomic operations to ensure validity of data accessed. In contrast, the slowpath operations may be executed to resolve contention between a transactional and non-transaction access contending for the same memory location. | 07-02-2009 |
| 20090241097 | METHOD AND APPARATUS TO IMPROVE EXECUTION OF A STORED PROGRAM - In one embodiment, the invention provides a method comprising determining metadata encoded in instructions of a stored program; and executing the stored program based on the metadata. | 09-24-2009 |
| 20090319753 | HYBRID LINEAR VALIDATION ALGORITHM FOR SOFTWARE TRANSACTIONAL MEMORY (STM) SYSTEMS - A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring ownership of meta-data associated with a data element, the meta-data is updated with an ownership reference to a transaction to enable efficient subsequent ownership tests. However, during validation, for some conditions, meta-data is updated from the ownership reference to a write entry reference to enable efficient validation. | 12-24-2009 |
| 20100005467 | THREAD SYNCHRONIZATION METHODS AND APPARATUS FOR MANAGED RUN-TIME ENVIRONMENTS - Thread synchronization methods and apparatus for managed run-time environments are disclosed. An example method to maintain state information for optimistically balanced synchronization of a lock of an object in a managed runtime environment disclosed herein comprises storing state information comprising a state of each pending optimistically balanced release operation corresponding to each pending optimistically balanced synchronization to be performed on the lock of the object, each pending optimistically balanced synchronization comprising respective paired acquisition and release operations between which an unknown number of unpaired locking operations are to occur, and modifying a first stored state of a first pending optimistically balanced release operation when a subsequent unpaired locking operation is performed on the lock, but not modifying any stored state of any pending optimistically balanced release, including the first stored state of a first pending optimistically balanced release operation, when a subsequent optimistically balanced synchronization is performed on the lock. | 01-07-2010 |
| 20100057740 | ACCELERATING A QUIESCENCE PROCESS OF TRANSACTIONAL MEMORY - A method to perform validation of a read set of a transaction is presented. In one embodiment, the method compares a read signature of a transaction to a plurality of write signatures associated with a plurality of transactions. The method determines based on the result of comparison, whether to update a local value of the transaction to a commit value of another transaction from the plurality of the transactions. | 03-04-2010 |
| 20100058344 | ACCELERATING A QUIESCENCE PROCESS OF TRANSACTIONAL MEMORY - A method to perform validation of a read set of a transaction is presented. In one embodiment, the method compares a read signature of a transaction to a plurality of write signatures associated with a plurality of transactions. The method determines based on the result of comparison, whether to update a local value of the transaction to a commit value of another transaction from the plurality of the transactions. | 03-04-2010 |
| 20100058362 | DEVICE, SYSTEM, AND METHOD OF EXECUTING A CALL TO A ROUTINE WITHIN A TRANSACTION - Device, system, and method of executing a call to a routine within a transaction. In some embodiments an apparatus may include a memory having stored thereon compiled code corresponding to a transaction, wherein the transaction includes at least one call to a first routine of a pair of first and second mutually inverse routines, and wherein the compiled code includes a call to a first wrapped routine replacing the call to the first routine; and a runtime library including wrapper code, wherein the wrapper code, when executed in response to the call to the first wrapped routine, results in executing the call to the first routine within the transaction and undoing the call to the first routine responsive to abort of the transaction. Other embodiments are described and claimed. | 03-04-2010 |
| 20100229043 | HARDWARE ACCELERATION FOR A SOFTWARE TRANSACTIONAL MEMORY SYSTEM - A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation costs. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction. | 09-09-2010 |
