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Ali Keshavarzi
Ali Keshavarzi, Portland, OR US
| Patent application number | Description | Published |
|---|---|---|
| 20080237675 | Capacitor, method of increasing a capacitance area of same, and system containing same - A capacitor includes a substrate ( | 10-02-2008 |
| 20080237678 | On-chip memory cell and method of manufacturing same - An on-chip memory cell comprises a tri-gate access transistor ( | 10-02-2008 |
| 20090003028 | Carbon nanotube fuse element - In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low current levels. | 01-01-2009 |
| 20100073994 | LEAKAGE COMPENSATION CIRCUIT FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELLS - A Dynamic Random Access Memory (DRAM) cell comprising a leakage compensation circuit. The leakage compensation circuit allows a compensation current from a source to flow to the memory cell storage node of the DRAM cell to compensate the leakage current from the memory cell storage node of the DRAM cell to improve retention time. | 03-25-2010 |
| 20100252812 | Methods of forming carbon nanotube transistors for high speed circuit operation and structures formed thereby - Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a channel region on a substrate, wherein the channel region comprises at least one CNT, forming at least one source/drain region adjacent the channel region, and then forming a gate electrode on the channel region, wherein a width of the gate electrode comprises about 50 percent to about 90 percent of a width of the contact region. | 10-07-2010 |
| 20110079837 | CAPACITOR, METHOD OF INCREASING A CAPACITANCE AREA OF SAME, AND SYSTEM CONTAINING SAME - A capacitor includes a substrate ( | 04-07-2011 |
Ali Keshavarzi, Los Altos Hills, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110291197 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance. | 12-01-2011 |
| 20110291200 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure. | 12-01-2011 |