| Patent application number | Description | Published |
|---|
| 20080212665 | System for monitoring the quality of a communications channel with mirror receivers - A system is presented that monitors the quality of a communications channel with mirror receivers. A first receiver and a second receiver, coupled in parallel with the first receiver, receive a data signal transmitted over the communications channel. The second receiver generates an output signal. A signal integrity (SI) processor manipulates the output signal in order to determine the quality of the communications channel. The SI processor samples a phase-shifted version of the output signal, which has a phase shifted relative to a zero reference phase, and analyzes the phase-shifted version of the output signal for bit errors. In an embodiment, the SI processor manipulates the output signal to extract an eye diagram indicative of the quality of the communications channel. The SI processor non-intrusively determines the quality of the communications channel using the second receiver. | 09-04-2008 |
| 20090190649 | Conditioning Circuit that Spectrally Shapes a Serviced Bit Stream - A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface module includes a line side interface, a board side interface, and a signal conditioning circuit. The line side interface includes a media coupler that receives the line side media, such as copper media or optical media. The board side interface couples the high-speed serial bit stream interface module to the PCB. A signal conditioning circuit communicatively couples to the line side interface and to the board side interface. The signal conditioning circuit receives an RX signal from the line side interface, conditions the RX signal, and provides the RX signal to the board side interface. The signal conditioning circuit receives a TX signal from the board side interface, conditions the TX signal, and provides the TX signal to the board side interface. | 07-30-2009 |
| 20100067567 | Multiple High-Speed Bit Stream Interface Circuit - A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB) or the communication ASIC to another communication ASIC. The high-speed bit stream interface includes a plurality of signal conditioning circuits. The signal conditioning circuits service each of an RX path and a TX path and include a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream. | 03-18-2010 |
| 20100221017 | Method and System for Optimum Channel Equalization From a SERDES to an Optical Module - Certain aspects of a method and system for optimum channel equalization between a host Serializer-Deserializer (SerDes) and an optical module may compensate and reduce dispersion loss along an electrical transmit path of a transmitter and an optical transmit path coupled to the transmitter via pre-emphasis. The data degradation as a result of the dispersion loss along the electrical transmit path of the transmitter and the optical transmit path coupled to the transmitter may be recovered by equalizing signals received via an electrical receive path of a receiver communicatively coupled to the transmitter. | 09-02-2010 |
| 20110249967 | Method and System for Adaptively Setting a Transmitter Filter for a High Speed Serial Link Transmitter - A communication device may be operable to determine, in an optical module, a signal quality associated with each of one or more host transmitter filters in a host circuit. The signal quality may be communicated from the optical module to the host circuit via a management interface. The communication device may control, in the host circuit, configuration of each of the host transmitter filters based on the signal quality. The communication device may be operable to determine, in the host circuit, a signal quality associated with each of one or more module transmitter filters in the optical module. The signal quality associated with each of the module transmitter filters may be communicated from the host circuit to the optical module via the management interface. The communication device may control, in the optical module, configuration of each of the module transmitter filters based on the signal quality. | 10-13-2011 |
| 20110283020 | METHOD AND SYSTEM FOR PHYSICAL LAYER AGGREGATION - Aspects of a method and system for physical layer aggregation are provided. A first portion of one or more circuits of a network device may be operable to implement media access control (MAC) functions, a second portion of the one or more circuits may be operable to perform physical layer aggregation, and a third portion of the one or more circuits may be operable to perform physical layer functions for communicating over a plurality of physical links. The first portion of the one or more circuits may be operable to encapsulate data into a packet comprising a preamble and convey the packet to the second portion of the one or more circuits. The second portion of the one or more circuits may be operable to fragment the packet into a plurality of fragment payloads and convey each of the fragment payloads to the third portion of the one or more circuits, wherein at least one of the plurality of fragment payloads comprises at least a portion of the preamble. The third portion of the one or more circuits may be operable to add a header to the fragment payloads to generate a corresponding plurality of fragments, and send the plurality of fragments over one or more of the plurality of physical links. | 11-17-2011 |
| 20120002713 | MULTI-PROTOCOL COMMUNICATIONS RECEIVER WITH SHARED ANALOG FRONT-END - According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol. | 01-05-2012 |
| 20120007640 | Multi-Channel Multi-Protocol Transceiver With Independent Channel Configuration Using Single Frequency Reference Clock Source - A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency. The voltage controlled oscillator is configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol. The selected output clock frequency is produced based on at least one of the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider. | 01-12-2012 |
