Patent application number | Description | Published |
20100015743 | ETCHED-FACET RIDGE LASERS WITH ETCH-STOP - A photonic device incorporates an epitaxial structure having an active region, and which includes a wet etch stop layer above, but close to, the active region. An etched-facet ridge laser is fabricated on the epitaxial structure by dry etching followed by wet etching. The dry etch is designed to stop before reading the depth needed to form the ridge. The wet etch completes the formation of the ridge and stops at the wet etch stop layer. | 01-21-2010 |
20100091810 | MULTI-LEVEL INTEGRATED PHOTONIC DEVICES - A laser and electroabsorption modulator (EAM) are monolithically integrated through an etched facet process. Epitaxial layers on a wafer include a first layer for a laser structure and a second layer for an EAM structure. Strong optical coupling between the laser and the EAM is realized by using two 45-degree turning mirrors to route light vertically from the laser waveguide to the EAM waveguide. A directional angled etch process is used to form the two angled facets. | 04-15-2010 |
20100099209 | MULTI-LEVEL INTEGRATED PHOTONIC DEVICES - A laser and electroabsorption modulator (EAM) are monolithically integrated through an etched facet process. Epitaxial layers on a wafer include a first layer for a laser structure and a second layer for an EAM structure. Strong optical coupling between the laser and the EAM is realized by using two 45-degree turning mirrors to route light vertically from the laser waveguide to the EAM waveguide. A directional angled etch process is used to form the two angled facets. | 04-22-2010 |
20110032967 | SINGLE LONGITUDINAL MODE LASER DIODE - A single-mode, etched facet distributed Bragg reflector laser includes an AlGaInAs/InP laser cavity, a front mirror stack with multiple Fabry-Perot elements, a rear DBR reflector, and a rear detector. The front mirror stack elements and the rear reflector elements include input and output etched facets, and the laser cavity is an etched ridge cavity, all formed from an epitaxial wafer by a two-step lithography and CAIBE process. | 02-10-2011 |
20110317734 | SPATIAL FILTERS - An etched-facet single lateral mode semiconductor photonic device is fabricated by depositing an anti reflective coating on the etched facet, and depositing a reflectivity modifying coating in a spatially controlled manner to modify the spatial performance of the emitted beam. | 12-29-2011 |
20120142123 | ALGAINN-BASED LASERS PRODUCED USING ETCHED FACET TECHNOLOGY - A process for fabricating AlGaInN-based photonic devices, such as lasers, capable of emitting blue light employs etching to form device waveguides and mirrors, preferably using a temperature of over 500° C. and an ion beam in excess of 500 V in CAIBE. | 06-07-2012 |
20120149141 | AlGaInN-Based Lasers Produced Using Etched Facet Technology - A process for fabricating AlGaInN-based photonic devices, such as lasers, capable of emitting blue light employs dry etching to form device waveguides and mirrors. The dry etching is preferably performed using a Chemically Assisted Ion Beam Etching (CAIBE) system. | 06-14-2012 |
Patent application number | Description | Published |
20120223681 | Electrodes, Batteries, Electrode Production Methods, and Battery Production Methods - Electrodes as well as electrode production methods are provided that can include a substrate with the substrate comprising non-conductive material. Batteries including electrodes of the disclosure are provided. Electricity storage methods are provided that can utilize the electrodes and/or batteries of the disclosure. | 09-06-2012 |
20130189547 | Battery Banks, Connector Assemblies, and Battery Connecting Methods - Methods for controlling the usage of individual and/or groups of batteries within a bank of batteries are provided. Methods for connecting batteries are also provided. Battery connector boards are provided. Battery banks are also provided. Battery connector assemblies are provided. | 07-25-2013 |
20130260235 | Electrodes, Batteries, Electrode Production Methods, and Battery Production Methods - Battery electrodes are provided that can include a conductive core supported by a polymeric frame. Methods for manufacturing battery electrodes are provided that can include: providing a sheet of conductive material; and framing the sheet of conductive material with a polymeric material. Batteries are provided that can include a plurality of electrodes, with individual ones of the electrodes comprising a conductive core supported by a polymeric frame. | 10-03-2013 |
Patent application number | Description | Published |
20090157976 | Network on Chip That Maintains Cache Coherency With Invalidate Commands - A network on chip (‘NOC’) that maintains cache coherency with invalidate commands, the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including a port on a router of the network through which is received an invalidate command, the invalidate command including an identification of a cache line, the invalidate command representing an instruction to invalidate the cache line, the router configured to send the invalidate command to an IP block served by the router; the router further configured to send the invalidate command horizontally and vertically to neighboring routers if the port is a vertical port; and the router further configured to send the invalidate command only horizontally to neighboring routers if the port is a horizontal port. | 06-18-2009 |
20110167296 | REGISTER FILE SOFT ERROR RECOVERY - Register file soft error recovery including a system that includes a first register file and a second register file that mirrors the first register file. The system also includes an arithmetic pipeline for receiving data read from the first register file, and error detection circuitry to detect whether the data read from the first register file includes corrupted data. The system further includes error recovery circuitry to insert an error recovery instruction into the arithmetic pipeline in response to detecting the corrupted data. The inserted error recovery instruction replaces the corrupted data in the first register file with a copy of the data from the second register file. | 07-07-2011 |
20120254548 | ALLOCATING CACHE FOR USE AS A DEDICATED LOCAL STORAGE - A method and apparatus dynamically allocates and deallocates a portion of a cache for use as a dedicated local storage. Cache lines may be dynamically allocated and deallocated for inclusion in the dedicated local storage. Cache entries that are included in the dedicated local storage may not be evicted or invalidated. Additionally, coherence is not maintained between the cache entries that are included in the dedicated local storage and the backing memory. A load instruction may be configured to allocate, e.g., lock, a portion of the data cache for inclusion in the dedicated local storage and load data into the dedicated local storage. A load instruction may be configured to read data from the dedicated local storage and to deallocate, e.g., unlock, a portion of the data cache that was included in the dedicated local storage. | 10-04-2012 |
20120254877 | TRANSFERRING ARCHITECTED STATE BETWEEN CORES - A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads. | 10-04-2012 |
20130086329 | ALLOCATING CACHE FOR USE AS A DEDICATED LOCAL STORAGE - A method and apparatus dynamically allocates and deallocates a portion of a cache for use as a dedicated local storage. Cache lines may be dynamically allocated and deallocated for inclusion in the dedicated local storage. Cache entries that are included in the dedicated local storage may not be evicted or invalidated. Additionally, coherence is not maintained between the cache entries that are included in the dedicated local storage and the backing memory. A load instruction may be configured to allocate, e.g., lock, a portion of the data cache for inclusion in the dedicated local storage and load data into the dedicated local storage. A load instruction may be configured to read data from the dedicated local storage and to deallocate, e.g., unlock, a portion of the data cache that was included in the dedicated local storage. | 04-04-2013 |
20130097411 | TRANSFERRING ARCHITECTED STATE BETWEEN CORES - A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads. | 04-18-2013 |
20130159669 | LOW LATENCY VARIABLE TRANSFER NETWORK FOR FINE GRAINED PARALLELISM OF VIRTUAL THREADS ACROSS MULTIPLE HARDWARE THREADS - A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core. | 06-20-2013 |
20130159799 | MULTI-CORE PROCESSOR WITH INTERNAL VOTING-BASED BUILT IN SELF TEST (BIST) - A method and circuit arrangement utilize scan logic disposed on a multi-core processor integrated circuit device or chip to perform internal voting-based built in self test (BIST) of the chip. Test patterns are generated internally on the chip and communicated to the scan chains within multiple processing cores on the chip. Test results output by the scan chains are compared with one another on the chip, and majority voting is used to identify outlier test results that are indicative of a faulty processing core. A bit position in a faulty test result may be used to identify a faulty latch in a scan chain and/or a faulty functional unit in the faulty processing core, and a faulty processing core and/or a faulty functional unit may be automatically disabled in response to the testing. | 06-20-2013 |