Patent application number | Description | Published |
20110222444 | SPLIT-BAND POWER AMPLIFIERS AND DUPLEXERS FOR LTE-ADVANCED FRONT END FOR IMPROVED IMD - A front end radio architecture (FERA) is disclosed that includes a transmitter block coupled to a power amplifier (PA) via first and second input terminals. A first split-band duplexer is coupled to a first output terminal of the PA and a second split-band duplexer is coupled to a second output terminal of the PA. The PA includes a first amplifier cell and a second amplifier cell that when coupled to the first and second split-band duplexers makes up first and second transmitter chains. Only one of the first and the second transmitter chains is active when a first carrier and a second carrier have a frequency offset that is less than an associated half duplex frequency within a same split-band duplex band, thus preventing third order inter-modulation (IMD) products from falling within an associated receive channel. Otherwise, the first and the second transmitter chains are both active. | 09-15-2011 |
20110291857 | METHOD OF POWER AMPLIFIER CALIBRATION - The exemplary embodiments include methods, computer readable media, and devices for calibrating a non-linear power detector of a radio frequency device based upon measurements of the non-linear power detector output and the associated power amplifier output level, and a set of data points that characterize a nominal non-linear power detector. The set of data points that characterize the nominal non-linear power detector is stored in a calibration system memory as nominal power detector output data. The measured non-linear power detector outputs, power amplifier output levels, and the nominal power detector output data is used to determine a power detector error function that characterizes the difference between the response of the non-linear power detector and the nominal non-linear power detector. The power detector error function and the nominal power detector output data are used to develop a calibrated power detector output data set that is stored in the non-linear power detector. | 12-01-2011 |
20120200473 | HARMONIC REJECTED ANTENNA SWITCH - The exemplary embodiments include a radio frequency antenna switch configured to reject harmonic frequencies. In addition, the harmonic-rejected radio frequencies of the radio frequency antenna switch may be tuned by use of a capacitor array. The capacitor array may be configured with fuse elements or by control logic. | 08-09-2012 |
20120281597 | RADIO FRONT END AND POWER MANAGEMENT ARCHITECTURE FOR LTE-ADVANCED - A front end radio architecture (FERA) with power management is disclosed. The FERA includes a first power amplifier (PA) block having a first-first PA and a first-second PA, and a second PA block having a second-first PA and a second-second PA. First and second modulated switchers are adapted to selectively supply power to the first-first PA and the second-first PA, and to supply power to the first-second PA and the second-second PA, respectively. The first and second modulated switchers have a modulation bandwidth of at least 20 MHz and are both suitable for envelope tracking modulation. A control system is adapted to selectively enable and disable the first-first PA, first-second PA, the second-first PA, and the second-second PA. First and second switches are responsive to control signals to route carriers and received signals between first and second antennas depending upon a selectable mode of operation such as intra-band or inter-band operation. | 11-08-2012 |
20120306572 | METHOD OF POWER AMPLIFIER CALIBRATION FOR AN ENVELOPE TRACKING SYSTEM - A method for power amplifier (PA) calibration for an envelope tracking system of a wireless device is disclosed. The method involves measuring an output power of a PA that is a part under test (PUT) at a predetermined input power. Another step includes calculating a gain equal to the output power of the PA divided by the predetermined input power. A next step involves calculating a gain correction by subtracting the calculated gain from a desired gain. Other steps include determining an expected supply voltage for the PA at the desired gain using the gain correction applied to a nominal curve of gain versus PA supply voltage, and then storing the expected supply voltage for the PA versus input power in memory. | 12-06-2012 |
20130113556 | VOLTAGE, CURRENT, AND SATURATION PREVENTION - In one embodiment, saturation of the control system of a power amplifier is limited by comparing a control voltage at a first control node against a scaled battery voltage, and then drawing an error current away from the first control node when the control voltage exceeds the scaled battery voltage. The first control node may be located after a trans-conductance amplifier in a feedback control system. | 05-09-2013 |
20130135043 | MULTIMODE RF AMPLIFIER SYSTEM - Multimode radio frequency (RF) amplifier systems and techniques are disclosed. In one embodiment, a multimode radio frequency (RF) amplifier system has a first RF amplifier and a second RF amplifier. The first RF amplifier may support a first RF communication standard. The second RF amplifier may support a second RF communication standard. The first RF amplifier includes an auxiliary circuit. The auxiliary circuit may provide a service or a utility to a second RF amplifier. For example, the auxiliary circuit may generate a supply voltage to power the second RF amplifier. | 05-30-2013 |
20140035673 | MULTIMODE DIFFERENTIAL AMPLIFIER BIASING SYSTEM - Differential power amplifier circuitry includes a differential transistor pair, an input transformer, and biasing circuitry. The base contact of each transistor in the differential transistor pair may be coupled to the input transformer through a coupling capacitor. The coupling capacitors may be designed to resonate with the input transformer about a desired frequency range, thereby passing desirable signals to the differential transistor pair while blocking undesirable signals. The biasing circuitry may include a pair of emitter follower transistors, each coupled at the emitter to the base contact of each one of the transistors in the differential transistor pair and adapted to bias the differential transistor pair to maximize efficiency and stability. | 02-06-2014 |
20140038675 | FRONT END RADIO ARCHITECTURE (FERA) WITH POWER MANAGEMENT - A front end radio architecture (FERA) with power management is disclosed. The FERA includes a first power amplifier (PA) block having a first-first PA for amplifying first-first signals and a first-second PA for amplifying first-second signals. Also included is a second PA block having a second-first PA for amplifying second-first signals and a second-second PA for amplifying second-second signals. At least one power supply is adapted to selectively supply power to the first-first PA and the second-second PA through a first path. The power supply is also adapted to selectively supply power to the first-second PA and the second-first PA through a second path. A control system is adapted to selectively enable and disable the first-first PA, the first-second PA, the second-first PA, and the second-second PA. | 02-06-2014 |
20140111275 | EFFICIENT POWER TRANSFER POWER AMPLIFIER (PA) ARCHITECTURE - An efficient power transfer power amplifier (PA) architecture is disclosed that includes a first PA, a first impedance transformation network (ITN) coupled to the first PA, a second PA, and a second ITN coupled to the second PA. A switching network having a plurality of load outputs along with a first switch input coupled to a first impedance output of the first ITN and a second switch input coupled to a second impedance output of the first ITN, a third switch input coupled to a third impedance output of the second ITN, and a fourth switch input coupled to a fourth impedance output of the second ITN. A control system is adapted to control the switching network to switch signals at the first, second, third, and fourth switch inputs such that select ones of the signals travel paths having matching impedances to loads coupled to the plurality of load outputs. | 04-24-2014 |
20140304442 | SERIAL BUS BUFFER WITH NOISE REDUCTION - Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface. | 10-09-2014 |
20140375390 | POWER AMPLIFIER WITH IMPROVED LOW BIAS MODE LINEARITY - Power amplifier circuitry includes a power amplifier including an input node and an output node, biasing circuitry, a selectable impedance network, and an input capacitor. The input capacitor is coupled to the input node of the power amplifier. The biasing circuitry is coupled to the input node of the power amplifier through the selectable impedance network. The power amplifier is operable in a low power operating mode and a high power operating mode. In the low power operating mode, the biasing circuitry delivers a first biasing current to the input node of the power amplifier, and a first impedance level of the selectable impedance is selected. In the high power operating mode, the biasing circuitry delivers a second biasing current to the input node of the power amplifier, and a second impedance level of the selectable impedance is selected. | 12-25-2014 |