Patent application number | Description | Published |
20090282381 | ELECTRONIC DESIGN AUTOMATION TOOL AND METHOD FOR OPTIMIZING THE PLACEMENT OF PROCESS MONITORS IN AN INTEGRATED CIRCUIT - An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position identifier coupled to the critical path/cell identifier and configured to identify a set of candidate positions for the PMs, (3) a cluster generator coupled to the critical path/cell identifier and configured to associate the critical cells to form clusters thereof and (4) a PM placement optimizer coupled to the candidate PM position identifier and the cluster generator and configured to place a PM within each of the clusters by selecting among the candidate positions. | 11-12-2009 |
20100095259 | Circuit Timing Analysis Incorporating the Effects of Temperature Inversion - Methods and apparatus for increasing the accuracy of timing characterization of a circuit including one or more cells in a cell library are provided. One method includes the steps of: performing cell library timing characterization for each of the cells in the circuit for at least first and second prescribed temperatures, the first and second temperatures corresponding to first and second PVT corners, respectively, in the cell library; calculating respective cell delays for the one or more cells in the circuit, the cell delay calculation being a function of temperature for each instance of the one or more cells; and incorporating the cell delay calculation into the timing characterization for each of the cells in the circuit to thereby increase the accuracy of the timing characterization. | 04-15-2010 |
20100095260 | Reducing Path Delay Sensitivity to Temperature Variation in Timing-Critical Paths - A method for reducing path delay sensitivity to temperature variation in a circuit is provided. The method includes the steps of: identifying at least one timing-critical path in the circuit, the path including a plurality of circuit cells coupled between an input and an output of the path; determining a temperature slope coefficient of the path; when the slope coefficient is negative, increasing the slope coefficient by controlling at least one characteristic of at least one of the cells in the path; and when the slope coefficient is positive, decreasing the slope coefficient by controlling at least one characteristic of at least one of the cells in the path. | 04-15-2010 |
20100153895 | TIMING ERROR SAMPLING GENERATOR, CRITICAL PATH MONITOR FOR HOLD AND SETUP VIOLATIONS OF AN INTEGRATED CIRCUIT AND A METHOD OF TIMING TESTING - A timing error sampling generator, a path monitor, an IC, a method of performing timing tests and a library of cells. In one embodiment, the timing error sampling generator includes: (1) a hold delay element having an input and an output and configured to provide a hold violation delayed signal at said output by providing a first predetermined delay to a clock signal received at said input, said first predetermined delay corresponding to a hold violation time for a path to be monitored and (2) a hold logic element having a first input coupled to said input of said hold delay element, a second input coupled to said output of said hold delay element and an output at which said hold logic element is configured to respond to said first and second inputs to provide a clock hold signal when logic levels at said first and second inputs are at a same level. | 06-17-2010 |
20100289112 | METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE CHIP-LEVEL IMPLEMENTATION PROCESS THROUGH AN OVER-CORE WINDOW ON A CHIP-LEVEL ROUTING LAYER - A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic. | 11-18-2010 |
20120017190 | IMPLEMENTING AND CHECKING ELECTRONIC CIRCUITS WITH FLEXIBLE RAMPTIME LIMITS AND TOOLS FOR PERFORMING THE SAME - An apparatus and a method of generating a flexible ramptime limit for an electronic circuit, a computer program product that performs the same method, and a method of manufacturing an electronic circuit employing a flexible ramptime limit is disclosed. In one embodiment, the method for generating a flexible ramptime limit includes: (1) calculating a frequency based ramptime limit for the electronic circuit, (2) obtaining a library based ramptime limit for the electronic circuit, (3) determining a minimum ramptime limit between the frequency based ramptime limit and the library based ramptime limit and (4) selecting the minimum ramptime limit as the flexible ramptime limit. | 01-19-2012 |
20120210287 | Circuit Timing Analysis Incorporating the Effects of Temperature Inversion - Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively; selecting one or more additional temperatures between the first and second temperatures; performing cell timing characterization for each process, voltage and temperature (PVT) corner at the one or more additional temperatures, as well as at the first and second temperatures; and performing timing sign-off for each PVT corner using the one or more additional temperatures, the timing sign-off being based at least in part on the timing characterization for each PVT corner. | 08-16-2012 |
20120278780 | TIMING ERROR SAMPLING GENERATOR AND A METHOD OF TIMING TESTING - A timing error sampling generator, a path monitor, an IC, a method of performing timing tests and a library of cells are provided. In one embodiment, the timing error sampling generator includes: (1) a hold delay element having an input and an output and configured to provide a hold violation delayed signal at said output by providing a first predetermined delay to a clock signal received at said input, said first predetermined delay corresponding to a hold violation time for a path to be monitored and (2) a hold logic element having a first input coupled to said input of said hold delay element, a second input coupled to said output of said hold delay element and an output at which said hold logic element is configured to respond to said first and second inputs to provide a clock hold signal when logic levels at said first and second inputs are at a same level. | 11-01-2012 |
20130043602 | METHOD AND APPARATUS OF CORE TIMING PREDICTION OF CORE LOGIC IN THE CHIP-LEVEL IMPLEMENTATION PROCESS THROUGH AN OVER-CORE WINDOW ON A CHIP-LEVEL ROUTING LAYER - A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic. | 02-21-2013 |
20140089881 | Circuit Timing Analysis Incorporating the Effects of Temperature Inversion - Methods and apparatus for increasing the accuracy of timing characterization of a circuit including at least one cell in a cell library are provided. One method includes the steps of: performing cell library timing characterization for the cell for prescribed first and second temperatures, the first and second temperatures corresponding to minimum and maximum temperatures of operation of the circuit, respectively; selecting one or more additional temperatures between the first and second temperatures; performing cell timing characterization for each process, voltage and temperature (PVT) corner at the one or more additional temperatures, as well as at the first and second temperatures; and performing timing sign-off for each PVT corner using the one or more additional temperatures, the timing sign-off being based at least in part on the timing characterization for each PVT corner. | 03-27-2014 |