Patent application number | Description | Published |
20090167317 | Apparatus And Method For Test, Characterization, And Calibration Of Microprocessor-Based And Digital Signal Processor-Based Integrated Circuit Digital Delay Lines - A circuit board with a processing unit and a delay line with a controllable number of delay elements fabricated thereon includes apparatus for testing and calibrating the delay line elements. In the test mode, a calibrated pulse is delayed by the delay line while determining the logic state of pulse at two times, the interval between the two times being the same as the pulse width. By adding delay elements, the period of the calibrated pulse as a function of number of delay elements can determine the delay of each delay element. In the calibration mode, the delay line is configured as a ring oscillator and the frequency of the ring oscillator as a function of number of delay elements provides the time delay for the individual elements. | 07-02-2009 |
20120319751 | HIGH RESOLUTION CAPTURE - The high resolution capture (HRCAP) of this invention enables time stamping of input signals with very high resolution without requiring high frequency sampling. This invention uses a capture delay line to time stamp an input edge signal as a fraction of the input signal sampling frequency. The capture delay line includes a first input receiving a synchronized signal and a second input receiving the input signal. These inputs propagate toward one another within a sequence of bit circuits. The meeting location within the sequence of bit circuits indicates a time of the input signal transition at a resolution greater than possible via the sampling frequency clock. | 12-20-2012 |
20120324318 | Processor Instructions to Accelerate Viterbi Decoding - Viterbi decoding may be performed on a microcontroller by initializing a state-metric array by executing load instructions to load state-metric data from a memory module into a set of registers in the microcontroller. Butterfly processing on the state-metric array is performed by executing Viterbi processing instructions fetched from a program storage module to manipulate the state-metric (SM) data in the set of registers for each Viterbi butterfly in a stage of Viterbi decoding to form a final set of state-metric data and trace bits. After completing each stage, a final set of state-metric data may be stored in the memory module by executing store instructions. | 12-20-2012 |
20120324321 | CO-HOSTED CYCLICAL REDUNDANCY CHECK CALCULATION - A co-hosted cyclical redundancy check (CRC) calculations system is arranged to use a processor to generate initial addresses for reading the data from a mirrored device that has address ranges over which a CRC result is to be calculated. An memory mapping unit detects when the initial address falls within an address range over which the CRC result is to be calculated. A read snoop unit snoops the data read from a mirrored memory that has data stored using a mirrored address. A CRC co-generator receives the snooped data read from mirrored memory and uses the snooped data read from the mirrored memory to calculate the CRC result. | 12-20-2012 |
20120331560 | Microcontroller with Secure Feature for Multiple Party Code Development - Multiple secure environments are established within a system on a chip (SoC) by defining a first secure region within a non-volatile memory in the SoC with a first set of parameters written into a predefined parameter region of the non-volatile memory. A second secure region within the non-volatile memory may be defined at a later time by a second set of parameters written into another predefined parameter region of the non-volatile memory. A security module is initialized each time the SoC is powered on by transferring the first set of parameters and the second set of parameters from the parameter region to the security module in a manner that does not expose the first set of parameters or the second set of parameters to a program being executed by the processor. The multiple secure regions of the SoC are enforced by the security module according to the parameter data. | 12-27-2012 |
20140129908 | VITERBI BUTTERFLY OPERATIONS - A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes registers in which each register is arranged to store a state metric for processing. The butterfly unit includes an array of butterfly elements where each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit. The constraint length multiplexer unit is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register. Transition bits can also be generated in response to the constraint length. | 05-08-2014 |