| Patent application number | Description | Published |
|---|
| 20080206958 | ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXIAL COMPRESSIVE STRAIN - The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer. | 08-28-2008 |
| 20080206965 | STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY - Disclosed herein is a method of preparing strained silicon comprising annealing a carbon-doped silicon-germanium (SiGe:C) alloy containing region disposed adjacent to a silicon region, wherein the lattice constant of the SiGe:C alloy after annealing is greater than that of the SiGe:C alloy prior to annealing. The method can be used to prepare articles including metal oxide semiconductor field effect transistor (MOSFET) devices. | 08-28-2008 |
| 20080217697 | CONTROL OF POLY-Si DEPLETION IN CMOS VIA GAS PHASE DOPING - A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein. | 09-11-2008 |
| 20080254594 | STRAINED SILICON CMOS ON HYBRID CRYSTAL ORIENTATIONS - Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si. | 10-16-2008 |
| 20080258220 | ION IMPLANTATION COMBINED WITH IN SITU OR EX SITU HEAT TREATMENT FOR IMPROVED FIELD EFFECT TRANSISTORS - This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants. | 10-23-2008 |
| 20080261055 | PREPARATION OF HIGH QUALITY STRAINED-SEMICONDUCTOR DIRECTLY-ON-INSULATOR SUBSTRATES - A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. Similarly, a method for forming thin to ultra-thin strain Si, SiC, or SiC/Si layers directly on insulator substrates having a strain content in the range of about 1-5% is further described | 10-23-2008 |
| 20080277690 | STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED p+ SILICON GERMANIUM LAYER - A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations. | 11-13-2008 |
| 20090117720 | STRAINED SEMICONDUCTOR-ON-INSULATOR BY Si:C COMBINED WITH POROUS PROCESS - A method of fabricating a strained semiconductor-on-insulator (SSOI) substrate is provided. The method includes first providing a structure that includes a substrate, a doped and relaxed semiconductor layer on the substrate, and a strained semiconductor layer on the doped and relaxed semiconductor layer. In the invention, the doped and relaxed semiconductor layer having a lower lattice parameter than the substrate. Next, at least the doped and relaxed semiconductor layer is converted into a buried porous layer and the structure including the buried porous layer is annealed to provide a strained semiconductor-on-insulator substrate. During the annealing, the buried porous layer is converted into a buried oxide layer. | 05-07-2009 |
| 20090134460 | STRAINED SEMICONDUCTOR-ON-INSULATOR (sSOI) BY A SIMOX METHOD - A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer. | 05-28-2009 |
| 20090298258 | QUASI-HYDROPHOBIC Si-Si WAFER BONDING USING HYDROPHILIC Si SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE - The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition. | 12-03-2009 |
