Patent application number | Description | Published |
20120105105 | Nonvolatile Logic Circuit - Semiconductor industry seeks to replace traditional volatile logic and memory devices with the improved nonvolatile devices. The increased demand for a significantly advanced, efficient, and nonvolatile data retention technique has driven the development of magnetic tunnel junctions (MTJs) employing a giant magneto-resistance (GMR). The present application relates to nonvolatile logic circuits with integrated MTJs and, in particular, concerns a nonvolatile spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct the nonvolatile logic circuits performing NOT, NOR, NAND and other logic functions. | 05-03-2012 |
20120155153 | Scalable Magnetic Memory Cell With Reduced Write Current - A magnetic memory cell comprising a magnetoresistive element including a free layer with a changeable orientation of a magnetization oriented substantially perpendicular to a layer plane in its equilibrium state, a pinned layer with a fixed orientation of a magnetization oriented substantially perpendicular to a layer plane, and a tunnel barrier layer disposed between the free and pinned layers; means for providing a bias magnetic field pulse along magnetic hard axis of both the free and pinned layers, means for providing a spin-polarized current pulse through the magnetoresistive element along magnetic easy axis of both the free layer and the pinned layer, wherein the orientation of magnetization in the free layer will be reversed by a collective effect of the bias magnetic field pulse and the spin-polarizing current pulse; and wherein the magnetoresistive element comprises at least one magnetic layer whose magnetization having a perpendicular orientation in its equilibrium state can be tilted by the bias magnetic field to facilitate the magnetization reversal in the free layer by the spin-polarized current. | 06-21-2012 |
20120155154 | Three-Dimensional Magnetic Random Access Memory With High Speed Writing - A magnetic random access memory with perpendicular magnetization comprising a selection transistor with a gate width, that is formed on a substrate and is electrically connected to a word line; a plurality of memory layers sequentially disposed above the substrate, wherein each of the plurality of the memory layers includes a plurality of magnetoresistive elements with perpendicular magnetization and wherein each of the plurality of the magnetoresistive elements comprises an element width and includes at least a pinned layer comprising a fixed magnetization, a free layer comprising a changeable magnetization, and a tunnel barrier layer residing between the pinned layer and the free layer; a plurality of conductor layers disposed alternately with the memory layers beginning with the memory layer positioned adjacent to the substrate, wherein each of the plurality of the conductor layers comprises a plurality of parallel bit lines intersecting the word line, and wherein the bit line is disposed adjacent to the free layer and is electrically connected with the magnetoresistive element; wherein the gate width is substantially larger than the element width, and wherein the magnetoresistive elements of the memory layer are electrically connected in parallel to the selection transistor. | 06-21-2012 |
20120155164 | Multibit Cell of Magnetic Random Access Memory With Perpendicular Magnetization - A multi-bit cell of magnetic random access memory comprises a magnetic tunnel junction element including a first and second free layer comprising a changeable magnetization oriented substantially perpendicular to a layer plane in its equilibrium state and a switching current, a first and second tunnel barrier layer, and a pinned layer comprising a fixed magnetization oriented substantially perpendicular to a layer plane, the pinned layer is disposed between the first and second free layers and is separated from the free layers by one of the tunnel barrier layers, a selection transistor electrically connected to a word line, and a bit line intersecting the word line. The magnetic tunnel junction element is disposed between the bit line and the selection transistor and is electrically connected to the bit line and the selection transistor, wherein the first and second free layers have substantially different switching currents. | 06-21-2012 |
20120257449 | High Density Magnetic Random Access Memory - A magnetic memory device that comprises a substrate, a memory cell including a magnetic tunnel junction which comprises a free ferromagnetic layer having a reversible magnetization direction directed perpendicular to the substrate, a pinned ferromagnetic layer having a fixed magnetization direction directed perpendicular to the substrate, and an insulating tunnel barrier layer disposed between the pinned and free layers, a first electrical circuit for applying a first current to a first conductor electrically coupled to the free layer to produce a bias magnetic field along a hard axis of the free layer, a second electrical circuit for applying a second current to a second conductor electrically coupled to the pinned layer to cause a spin momentum transfer in the free layer, wherein magnitudes of the bias magnetic field and spin momentum transfer in combination exceed a threshold and thus reverse the magnetization direction of the free layer. | 10-11-2012 |
20120261777 | Magnetoresistive Element and Method of Manufacturing the Same - A magnetoresistive element (and method of fabricating the magnetoresistive element) that includes a free ferromagnetic layer comprising a first reversible magnetization direction directed substantially perpendicular to a film surface, a pinned ferromagnetic layer comprising a second fixed magnetization direction directed substantially perpendicular to the film surface, and a nonmagnetic insulating tunnel barrier layer disposed between the free ferromagnetic layer and the pinned ferromagnetic layer, wherein the free ferromagnetic layer, the tunnel barrier layer, and the pinned ferromagnetic layer have a coherent body-centered cubic (bcc) structure with a (001) plane oriented, and a bidirectional spin-polarized current passing through the coherent structure in a direction perpendicular to the film surface reverses the magnetization direction of the free ferromagnetic layer. | 10-18-2012 |
20120281465 | High Density Magnetic Random Access Memory - One embodiment of a magnetic memory device comprises a substrate and a plurality of planar memory arrays stacked on the substrate, each memory array includes a plurality of parallel first conductive lines, each first conductive line includes a ferromagnetic cladding, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of magnetic tunnel junctions, each magnetic tunnel junction has a controllable electrical resistance, is disposed at an intersection region and electrically coupled to one of the first conductive lines at its first end and to one of the second conductive lines at its second end. The electrical resistance of the magnetic tunnel junction is controlled by a joint effect of a spin-polarized current running between the first and second ends and a bias magnetic field applied simultaneously to said each magnetic tunnel junction. Other embodiments are described and shown. | 11-08-2012 |
20120306536 | Nonvolatile Full Adder Circuit - A nonvolatile full adder circuit comprising a full adder electrical circuitry comprising three input terminals for receiving two input and carry-in signals, a sum output terminal, and an carry-out output terminal; first and second nonvolatile memory elements electrically coupled to the first and second output terminal, respectively at their first ends and to an intermediate voltage source at their second ends. The nonvolatile memory elements comprise two stable logic states. A logic state each of the of the nonvolatile memory elements is controlled by a bidirectional electrical current running between its first and second ends. The full adder circuitry is electrically coupled to a high voltage source at its first source terminal and to a low voltage source at its second source terminal, wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source. | 12-06-2012 |
20120307549 | Nonvolatile Latch Circuit - A nonvolatile latch circuit that includes a logic circuitry comprising at least an input terminal, a clock terminal, an output terminal, and a nonvolatile memory element. The logic circuitry is electrically coupled to a high voltage source at a first source terminal and to a low voltage source at a second source terminal. The nonvolatile memory element is electrically coupled to the output terminal at a first end and to a intermediate voltage source at a second end. A logic state of the latch circuit responds to an input signal during an active period of a clock signal. A logic state of the nonvolatile memory element is controlled by a bidirectional current running between the first and second ends. An electrical potential of the intermediate voltage source is higher than that of the low voltage source but lower than that of the high voltage source. | 12-06-2012 |
20130078482 | Scalable Magnetoresistive Element - A magnetoresistive element that includes a free ferromagnetic layer comprising a reversible magnetization directed substantially perpendicular to a film surface, a pinned ferromagnetic layer comprising a fixed magnetization directed substantially perpendicular to the film surface, and a tunnel barrier layer disposed between the free and pinned ferromagnetic layers, wherein the free and pinned layers contain at least one element selected from the group consisting of Fe, Co, and Ni, at least one element selected from the group consisting of V, Cr, and Mo, and at least one element selected from the group consisting of B, P, C, and Si, and wherein the free layer, the tunnel barrier layer, and the pinned layer have a coherent body-centered cubic structure with a (001) plane oriented, and a bidirectional spin-polarized current passing through the coherent structure in a direction perpendicular to the film surface reverses a magnetization direction of the free layer. | 03-28-2013 |
20130250669 | Scalable Magnetic Memory Cell With Reduced Write Current - One embodiment of a magnetic random access memory includes a magnetic memory cell comprising a magnetoresistive element including a free ferromagnetic layer comprising a reversible magnetization direction directed substantially perpendicular to a film plane in its equilibrium state, a pinned ferromagnetic layer comprising a fixed magnetization direction directed substantially perpendicular to the film plane, a tunnel barrier layer disposed between the free and pinned layers, and an assist ferromagnetic layer disposed adjacent to the free layer; means for providing a bias magnetic field pulse along a magnetic hard axis of the free layer, means for providing a spin-polarized current pulse through the magnetoresistive element in a direction perpendicular to the film plane, wherein the magnetization direction in the free layer is reversed by a collective effect of the bias magnetic field pulse and the spin-polarizing current pulse. Other embodiments are described and shown. | 09-26-2013 |
20130308373 | Nonvolatile Latch Circuit - One embodiment of a nonvolatile latch circuit comprises a latch circuitry configurated to temporarily hold data and comprising a first output terminal, the latch circuitry is coupled to a high voltage source at a first source terminal and to a low voltage source at a second source terminal, and a first nonvolatile memory element configurated to store said data and comprising a low resistance and a high resistance. The first memory element is connected in-series with a first transistor and coupled between the first output terminal and an intermediate voltage source. The resistance of the first memory element is changed by a bidirectional current running between the first output terminal and the intermediate voltage source, wherein an electrical potential of the intermediate voltage source is higher than that of the low voltage source but lower than that of the high voltage source. Other embodiments are described and shown. | 11-21-2013 |
20140103470 | Multibit Cell of Magnetic Random Access Memory with Perpendicular Magnetization - A multi-bit cell of magnetic random access memory comprises a magnetoresistive element including first and second free layers, each free layer comprising a reversible magnetization direction directed substantially perpendicular to a layer plane in its equilibrium state and a switching current, first and second tunnel barrier layers, and a pinned layer comprising a fixed magnetization direction directed substantially perpendicular to the layer plane, the pinned layer is disposed between the first and second free layers and is separated from the free layers by one of the tunnel barrier layers; a selection transistor electrically connected to a word line, and a bit line intersecting the word line; the magnetoresistive element is disposed between the bit line and the selection transistor and is electrically connected to the bit line and the selection transistor, wherein the first and second free layers have substantially different switching currents. | 04-17-2014 |
20140159770 | Nonvolatile Logic Circuit - One embodiment of a nonvolatile logic circuit includes a logic circuit comprising a first source terminal, a second source terminal, at least one input terminal, and an output terminal to temporarily store a logic state with a power dependent status, a high voltage source coupled to the first source terminal, a low voltage source coupled to the second source terminal, an intermediate voltage source comprising an electrical potential higher than that of the low voltage source but lower than that of the high voltage source, and a nonvolatile reversible resistance element coupled to the output terminal at a first end and to the intermediate voltage source at a second end. The nonvolatile reversible resistance element preserves the logic state of the logic circuit which is controlled by an input signal applied to the at least one input terminal. Other embodiment are described and shown. | 06-12-2014 |
20140252438 | Three-Dimensional Magnetic Random Access Memory With High Speed Writing - One embodiment of a magnetic random access memory includes a magnetic memory cell comprising a transistor disposed on a substrate, electrically coupled to a first conductive line and comprising a gate width; a plurality of magnetoresistive elements, each magnetoresistive element comprising an element width, a pinned magnetic layer comprising a fixed magnetization direction directed perpendicular to the substrate, a free magnetic layer comprising a reversible magnetization direction directed perpendicular to the substrate, and a tunnel barrier layer residing between the pinned and free layers; and a plurality of parallel second conductive lines overlapping the first conductive line. The plurality of the parallel second lines is independently electrically coupled to the plurality of magnetoresistive elements at first terminals, and the plurality of magnetoresistive elements is jointly electrically coupled to the transistor at second terminals, wherein the gate width is substantially larger than the element width. Other embodiments are described and shown. | 09-11-2014 |