| Patent application number | Description | Published |
|---|
| 20090066724 | GRAPHICS DISPLAY SYSTEM WITH GRAPHICS WINDOW CONTROL MECHANISM - A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip processes graphics images organized as windows. The chip obtains data that describes the windows, sorts the data according to the depth of the window on the display, transfers graphics images from memory, and blends the graphics images using alpha values associated with the graphics images. | 03-12-2009 |
| 20090129481 | SYSTEM AND METHOD FOR TRANSCODING ENTROPY-CODED BITSTREAMS - A system and method for transcoding an entropy-coded bitstream is presented herein. The syntax elements of the entropy-coded bitstream are decoded and transcoded into a second format. The second format can comprise a simpler format for decoding. The foregoing advantageously alleviates the processing requirements for the video decompression engine. | 05-21-2009 |
| 20090282172 | MEMORY ACCESS ENGINE HAVING MULTI-LEVEL COMMAND STRUCTURE - A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer field points to one of the DMA command lists. The sequence field holds a sequence value. A DMA engine accesses an entry in the command queue and then accesses the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry. The DMA engine performs the DMA operations specified by the accessed DMA commands. The DMA engine makes available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed. In one embodiment, the command queue is part of the DMA engine. | 11-12-2009 |
| 20100013993 | PULLDOWN FIELD DETECTOR - A system and method for detecting the presence and location of pull-down fields in a video field stream. Various aspects of the present invention may comprise method steps and circuit structure for generating an array of variance indications, each of which represents a degree of variance between two video fields in the video field stream. Various aspects may comprise comparing the array of variance indications to a pattern to detect a pull-down field in the video field stream. Various aspects may comprise comparing corresponding portions of video fields and generating a histogram of differences between the corresponding portions. Various aspects may comprise generating an indication of variance of the histogram and analyzing the indication of variance. Various aspects may comprise analyzing an array of such indications of variance and may comprise comparing the array of such indications to a pattern or plurality of patterns. | 01-21-2010 |
| 20100060641 | VIDEO AND GRAPHICS SYSTEM WITH SQUARE GRAPHICS PIXELS - A video and graphics system provides square graphics pixels to blend images having 640×480 pixels, such as graphics images provided by some set top boxes and intended to be displayed at a 12.27 MHz display sample rate, with images having 704×480 pixels, such as ITU-R 601 compliant images such as NTSC SDTV images, having oblong pixels and displayed at a 13.5 MHz display sample rate. A sample rate converter including a multi-phase-multi-tap filter is used to generate square pixels. The multi-phase-multi-tap filter provides a good balance of sharpness, smoothness, anti-aliasing and reduced ringing. The multi-phase-multi-tap filter can also be used to convert images having 320×480 pixels to images having 704×480 pixels. The multi-tap filter can be used for scan rate conversion of graphics or video images for HDTV or SDTV applications. | 03-11-2010 |
| 20100110106 | VIDEO AND GRAPHICS SYSTEM WITH PARALLEL PROCESSING OF GRAPHICS WINDOWS - A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream. | 05-06-2010 |
| 20100171761 | GRAPHICS DISPLAY SYSTEM WITH ANTI-FLUTTER FILTERING AND VERTICAL SCALING FEATURE - A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video. | 07-08-2010 |
| 20100171762 | GRAPHICS DISPLAY SYSTEM WITH ANTI-FLUTTER FILTERING AND VERTICAL SCALING FEATURE - A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video. | 07-08-2010 |
| 20110122941 | VIDEO DECODING SYSTEM SUPPORTING MULTIPLE STANDARDS - System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline. | 05-26-2011 |
