| Patent application number | Description | Published |
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| 20080320066 | Cryptographic random number generator using finite field operations - An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment. | 12-25-2008 |
| 20090158118 | CONFIGURABLE REED-SOLOMON DECODER BASED ON MODIFIED FORNEY SYNDROMES - A method of configurable decoding is disclosed. The method generally includes the steps of (A) receiving a variable value in a configuration signal, (B) calculating a plurality of first syndromes corresponding to a particular codeword of a plurality of codewords received in an input signal, the particular codeword having a plurality of information symbols and a plurality of parity symbols coded such that up to a fixed value of a plurality of errors in the particular codeword are correctable, the fixed value being greater than the variable value, (C) transforming the first syndromes into a plurality of second syndromes such that no greater than the variable value of the errors in the particular codeword are correctable and (D) generating an intermediate signal carrying the second syndromes. | 06-18-2009 |
| 20090243657 | METHODS AND APPARATUS FOR FAST UNBALANCED PIPELINE ARCHITECTURE - Methods and apparatus are provided for a fast unbalanced pipeline architecture. A disclosed pipeline buffer comprises a plurality of memory registers connected in series, each of the plurality of memory registers, such as flip-flops, having an enable input and a clock input; and a controlling memory register having an output that drives the enable inputs of the plurality of memory registers, whereby a predefined binary value on an input of the controlling memory register shifts values of the plurality of memory registers on a next clock cycle. A plurality of the disclosed pipeline buffets can be configured in a multiple stage configuration. At least one of the plurality of memory registers can comprise a locking memory register that synchronizes the pipeline buffer. The pipeline buffer can optionally include a delay gate to delay a clock signal and an inverter to invert the delayed clock signal. The clock signal can be delayed by the delay gate such that an output of the pipeline buffer is applied to a next stage of a pipeline buffer at a correct time. | 10-01-2009 |
| 20090281969 | Decision Tree Representation of a Function - An arbitrary function may be represented as an optimized decision tree. The decision tree may be calculated, pruned, and factored to create a highly optimized set of equations, much of which may be represented by simple circuits and little, if any, complex processing. A circuit design system may automate the decision tree generation, optimization, and circuit generation for an arbitrary function. The circuits may be used for processing digital signals, such as soft decoding and other processes, among other uses. | 11-12-2009 |
| 20090287980 | Computational Architecture for Soft Decoding - A device for soft decoding contains a set of operational elements, each being capable of performing one of several different functions. The operational elements may be dynamically configured with input and output connections to registers, memory locations, and other operational elements to perform various steps in a soft decoding scheme. In many cases, the operational elements may be configured to operate in a pipeline mode where many sequences of operations may be performed in parallel. Some embodiments may be reconfigured at each clock cycle to perform different steps during a decoding operation. The device may be used to perform several different soft decoding schemes with the flexibility of a programmable processor but the throughput of a hardware implementation. | 11-19-2009 |
| 20090309770 | METHODS AND APPARATUS FOR PROGRAMMABLE DECODING OF A PLURALITY OF CODE TYPES - Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network. The communications network can comprise, for example, a cross-bar switch and/or one or more first-in-first-out buffers. | 12-17-2009 |
| 20100030835 | Variable Node Processing Unit - A variable node processing unit with N+1 inputs, having at least a first bank of two-input adders and a separate last bank of two-input adders, where the banks of adders are disposed in series. | 02-04-2010 |
| 20100031127 | SCHEME FOR ERASURE LOCATOR POLYNOMIAL CALCULATION IN ERROR-AND-ERASURE DECODER - A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial. | 02-04-2010 |
| 20100162071 | CIRCUITS FOR IMPLEMENTING PARITY COMPUTATION IN A PARALLEL ARCHITECTURE LDPC DECODER - A parity unit circuit for use in a parallel, pipelined, low density parity check (LDPC) decoder that implements an iterative, min-sum, message passing LDPC algorithm. The parity unit provides a memory logic block for storing information relating to a current and next iteration of the LDPC computations and includes a “compute | 06-24-2010 |
| 20110099454 | Low Complexity LDPC Encoding Algorithm - A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B′x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form | 04-28-2011 |
