| Patent application number | Description | Published |
|---|
| 20080256303 | Cache memory - An apparatus for processing data comprises a cache memory having a plurality of cache rows each operable to store a cache line of data values, a memory management unit responsive to a page table entry to control access to a corresponding group of memory addresses forming a memory page, and a cache controller coupled to said cache memory and responsive to a cache miss to trigger a line fill operation to store data values into a cache row. The cache controller is responsive to a cache line size specifier associated with at least one page table entry to vary the number of data values within a cache line fetched in a line fill operation in dependence upon said cache line size specifier. Accordingly, by associating cache line size specifiers with page table entries, the number of data values to be stored in a line fill operation can be controlled on a memory page basis, which is advantageous because data values within the same page of memory are likely to be subject to similar types of access behaviour in the cache. Additionally, controlling cache line size on a page basis is more efficient, in terms of computation and storage, than controlling cache line size on a cache row or virtual address basis. | 10-16-2008 |
| 20090287865 | Interconnect - A method, an interconnect and a system for processing data is disclosed. The method comprises the steps of: a) receiving a request to perform a data transaction between a master unit and a slave unit, b) receiving an indication of a quality of service requirement associated with said data transaction; c) determining an interconnect quality of service level achievable when transmitting said data transaction over the interconnect logic having regard to any other pending data transactions which are yet to be issued; d) determining a slave quality of service level achievable when responding to said data transaction once received by said slave unit from said interconnect logic; and e) determining whether the combined interconnect quality of service level and the slave quality of service level fails to achieve the quality of service requirement and, if so, reordering the pending data transactions to enable the quality of service requirement of each data transaction to be achieved. Hence, arbitration between data transactions occurs prior to those transactions being provided to the interconnect. It will be appreciated that this enables pending data transactions to be systematically reordered and the quality of service level for each of these reordered data transactions to be accurately calculated to ensure that the quality of service requirement for each of those data transactions is achieved. Accordingly, this enables all aspects of quality of service to be budgeted together and true end-to-end quality of service may be determined for each data transaction. | 11-19-2009 |
| 20090319718 | MEMORY CONTROLLER ADDRESS MAPPING SCHEME - A data processing system is provided with a memory controller ( | 12-24-2009 |
