Patent application number | Description | Published |
20090158107 | SYSTEM-ON-CHIP WITH MASTER/SLAVE DEBUG INTERFACE - A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface and a user interface. The master/slave debug interface on the master SOC IC is a bidirectional debug interface operable to send and receive debug data between the SOC ICs and an external host system. The host system is connected to the at least one of the plurality of SOC ICs via the user interface. | 06-18-2009 |
20090187747 | SYSTEM AND METHOD FOR TRACING INSTRUCTION POINTERS AND DATA ACCESS - A system and method for tracing instruction pointers and data access is disclosed. In one embodiment the system includes a plurality of trace units including at least one first trace unit configured to perform an instruction pointer trace, and at least one second trace unit configured to perform a data trace. A multiplexer is connected between the plurality of processor cores and the plurality of trace units. | 07-23-2009 |
20090210638 | ADDRESS MAPPING OF PROGRAM CODE AND DATA IN MEMORY - A system for mapping information addresses in a memory. The system includes a memory wherein each byte is mapped to a plurality of unique addresses and a microprocessor for assigning at least one of the unique addresses to the information. The information can be program code fragments and/or data. Also disclosed is a method for mapping information addresses in a memory utilizing such a system. The method includes mapping each byte of memory into a plurality of unique addresses and assigning at least one of the unique addresses to the information. | 08-20-2009 |
20090222254 | SYSTEM AND METHOD FOR INTEGRATED CIRCUIT EMULATION - A system and method for integrated circuit emulation. One embodiment provides a system for in-circuit emulation of an integrated circuit device with program-controlled components. The system includes an integrated circuit device with program-controlled components used in a system for normal operation. The integrated circuit device having at least one program-controlled emulation unit emulating at least one of the program-controlled components of the integrated circuit device, and at least one statistics memory for storing statistical data of the program-controlled emulation unit during emulation. | 09-03-2009 |
20090276665 | APPARATUS, SYSTEM, AND METHOD OF EFFICIENTLY UTILIZING HARDWARE RESOURCES FOR A SOFTWARE TEST - Apparatus, system and method of efficiently utilizing hardware resources for a software test in system having at least one redundant component, at least a part of which is used for the software test. | 11-05-2009 |
20100229038 | System and Method for Testing a Module - In an embodiment, a system is disclosed. The system has a bus interface port, a selection circuit coupled to the bus interface port, a first bus interface circuit coupled to the selection circuit and a second bus interface circuit coupled to the selection circuit. The selection circuit is configured to select between the first bus interface circuit and the second bus interface circuit. The system also has an initialization circuit configured to detect a first codeword written to the bus interface port, and activate the second bus interface circuit if the first codeword is detected. | 09-09-2010 |
20110041010 | SYSTEM-ON-CHIP WITH MASTER/SLAVE DEBUG INTERFACE - A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface. The master/slave debug interface on the master SOC IC is a bidirectional debug interface operable to send and receive debug data between the SOC ICs and an external host system. | 02-17-2011 |
20110138231 | HIGH COMPRESSION PROGRAM FLOW TRACE - A system and method provides for generating high compression program flow trace data by generating first program flow trace data whenever a conditional branch instruction of a program is executed by a CPU, generating second program flow trace data whenever an indirect branch instruction of a subset of indirect branch instructions is executed by the CPU, and generating third program flow trace data whenever a stack for storing instruction addresses of the program is manipulated, the manipulation occurring after a CALL instruction to a function or subroutine of the program is executed by the CPU and before a RET instruction is executed by the CPU. The subset of indirect branch instructions excludes RET indirect branch instructions of any function or subroutine for which the stack is not manipulated after a CALL instruction to the functions or subroutines is executed by the CPU and before the RET instruction is executed by the CPU. | 06-09-2011 |
20120089810 | Apparatus and Method for Formatting and Preselecting Trace Data - The invention relates to a method and apparatus for formatting and preselecting trace data, and includes a trace message generator, an address checker, and a memory connected to the trace message generator and address checker. The trace message generator is configured to receive an address and associated data and generate a trace message with the associated data for the received address. The address checker is configured to receive the address, check the received address with the aid of the memory, and generate an output signal that indicates whether or not the trace message generated for the address is intended to be stored. The memory is configured to receive the trace message generated by the trace message generator, receive the output signal generated by the address checker, and store the received trace message if the output signal indicates that the trace message is intended to be stored. | 04-12-2012 |
20120260131 | SYSTEM-ON-CHIP WITH MASTER/SLAVE DEBUG INTERFACE - A System-on-Chip (SOC) debugging system comprising a plurality of SOCs connected to a shared bus, at least one of the plurality of SOCs being a master SOC and comprising a master/slave debug interface, wherein the master/slave debug interface is a bidirectional debug interface configured to initiate transactions on the shared bus and operable to send and receive debug data between the SOCs, wherein the debug data comprises trace data. | 10-11-2012 |
20120266029 | ARRANGEMENT FOR PROCESSING TRACE DATA INFORMATION, INTEGRATED CIRCUITS AND A METHOD FOR PROCESSING TRACE DATA INFORMATION - An arrangement for processing trace data information is provided, the arrangement including, a chip including one or more memory circuits configured to store trace data information relating to a series of instructions, and a trace data information port configured to provide off-chip access to the trace data information; and a direct memory access controller circuit configured to control the transportation of trace data information from the one or more memory circuits to the trace data information port. | 10-18-2012 |
20130124901 | Embedded Voltage Regulator Trace - One embodiment of the present invention relates to a power and trace profiling system. The system includes a microcontroller based device having a voltage regulator. Additionally, the microcontroller based device is configured to receive a supply power. A system analyzer is configured to receive power profiles from the power profiler and trace profiles from the system profiler. The system analyzer is configured to identify power reduction modifications based on the power profiles and the trace profiles. | 05-16-2013 |
20130185601 | Compact Function Trace - In accordance with one aspect of the invention, a system for generating compact function trace data for leaf functions includes a central processing unit (CPU), configured to output program flow information needed for generating a program flow trace, and a trace unit, coupled to the CPU. The trace unit is configured to receive the program flow information from the CPU for generating compact function trace data. The trace unit further comprises a first output mode and a second output mode and is further configured to select either the first output mode or the second output mode for generating compact function trace data. | 07-18-2013 |
20140095846 | TRACE BASED MEASUREMENT ARCHITECTURE - A method for performing trace based measurement for a plurality of CPUs in parallel includes receiving a signal to perform a CPU parallel trace mode and enabling a parallel trace mode multiplexer to output all trace data, representing all data writes to the local memory, to a single observation unit. In one embodiment, the single observation unit is a processor observation block (POB), and in another embodiment, a bus observation block (BOB). If the single observation unit is a BOB, then the parallel trace mode multiplexer first routes the local memory data trace through a BOB adaptation layer to convert the CPU trace output data to data which is understood by the BOB. | 04-03-2014 |
20140156137 | Lightweight Trace Based Measurement Systems and Methods - An automotive electronics system includes an electronic control unit and a trace adapter. The electronic control unit is configured to receive measurement signals and provide control signals. Additionally, the electronic control unit is configured to generate or provide trace signals by replacing original instructions in a binary image with trace instructions. The trace instructions are functionally equivalent, but trigger providing the trace signals. The trace adapter is coupled to the electronic control unit. The trace adapter is configured to obtain the trace signals from the electronic control unit. | 06-05-2014 |
20140164848 | TRACING INSTRUCTION POINTERS AND DATA ACCESSES - A system for tracing instruction pointers and data accesses in a plurality of processor cores includes a plurality of trace units. The plurality of trace units include at least one first trace unit configured to perform an instruction pointer trace and at least one second trace unit configured to perform a data trace. The system includes a multiplexer coupled between the plurality of processor cores and the plurality of trace units. The multiplexer is configured to selectively connect one trace unit of the plurality of trace units to one processor core of the plurality of processor cores. The multiplexer is configured during run time based on one of hardware triggers and software. | 06-12-2014 |
20140189437 | Multi-Tier Trace - The disclosure relates to methods and systems for trace solutions in a computer processing system. More specifically, the disclosure relates to methods and systems for a multi-tier trace architecture. A method for separating raw trace data includes receiving raw trace data from one of more CPUs and/or busses in the system, separating the raw trace data into high bandwidth trace information (HBTI) and low bandwidth trace information (LBTI), recording the HBTI on an on-chip trace buffer until a specific event is triggered, and providing in parallel the LBTI over an off-chip trace interface. In one embodiment, the raw trace data are provided to a separate HBTI trace unit and a separate LBTI respectively. The HBTI trace unit processes the HBTI and generates a HBTI message, and the LBTI trace unit processes the LBTI and generates a LBTI message. | 07-03-2014 |
20140239987 | System and Method for Determining Operational Robustness of a System on a Chip - A system and method for determining operational robustness of a system on a chip (SoC) includes modifying one or more internal states of the SoC, during operation of the SoC, to mimic an effect which one or more disturbances have on the SoC, generating one or more signal traces that correspond to at least one internal state of the SoC after modifying the one or more internal states of the SoC, and determining if the operation of the SoC is stable based on the one or more generated signal traces. | 08-28-2014 |