| Patent application number | Description | Published |
|---|
| 20090158107 | SYSTEM-ON-CHIP WITH MASTER/SLAVE DEBUG INTERFACE - A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface and a user interface. The master/slave debug interface on the master SOC IC is a bidirectional debug interface operable to send and receive debug data between the SOC ICs and an external host system. The host system is connected to the at least one of the plurality of SOC ICs via the user interface. | 06-18-2009 |
| 20090187747 | SYSTEM AND METHOD FOR TRACING INSTRUCTION POINTERS AND DATA ACCESS - A system and method for tracing instruction pointers and data access is disclosed. In one embodiment the system includes a plurality of trace units including at least one first trace unit configured to perform an instruction pointer trace, and at least one second trace unit configured to perform a data trace. A multiplexer is connected between the plurality of processor cores and the plurality of trace units. | 07-23-2009 |
| 20090210638 | ADDRESS MAPPING OF PROGRAM CODE AND DATA IN MEMORY - A system for mapping information addresses in a memory. The system includes a memory wherein each byte is mapped to a plurality of unique addresses and a microprocessor for assigning at least one of the unique addresses to the information. The information can be program code fragments and/or data. Also disclosed is a method for mapping information addresses in a memory utilizing such a system. The method includes mapping each byte of memory into a plurality of unique addresses and assigning at least one of the unique addresses to the information. | 08-20-2009 |
| 20090222254 | SYSTEM AND METHOD FOR INTEGRATED CIRCUIT EMULATION - A system and method for integrated circuit emulation. One embodiment provides a system for in-circuit emulation of an integrated circuit device with program-controlled components. The system includes an integrated circuit device with program-controlled components used in a system for normal operation. The integrated circuit device having at least one program-controlled emulation unit emulating at least one of the program-controlled components of the integrated circuit device, and at least one statistics memory for storing statistical data of the program-controlled emulation unit during emulation. | 09-03-2009 |
| 20090276665 | APPARATUS, SYSTEM, AND METHOD OF EFFICIENTLY UTILIZING HARDWARE RESOURCES FOR A SOFTWARE TEST - Apparatus, system and method of efficiently utilizing hardware resources for a software test in system having at least one redundant component, at least a part of which is used for the software test. | 11-05-2009 |
| 20100229038 | System and Method for Testing a Module - In an embodiment, a system is disclosed. The system has a bus interface port, a selection circuit coupled to the bus interface port, a first bus interface circuit coupled to the selection circuit and a second bus interface circuit coupled to the selection circuit. The selection circuit is configured to select between the first bus interface circuit and the second bus interface circuit. The system also has an initialization circuit configured to detect a first codeword written to the bus interface port, and activate the second bus interface circuit if the first codeword is detected. | 09-09-2010 |
| 20110041010 | SYSTEM-ON-CHIP WITH MASTER/SLAVE DEBUG INTERFACE - A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface. The master/slave debug interface on the master SOC IC is a bidirectional debug interface operable to send and receive debug data between the SOC ICs and an external host system. | 02-17-2011 |
| 20110138231 | HIGH COMPRESSION PROGRAM FLOW TRACE - A system and method provides for generating high compression program flow trace data by generating first program flow trace data whenever a conditional branch instruction of a program is executed by a CPU, generating second program flow trace data whenever an indirect branch instruction of a subset of indirect branch instructions is executed by the CPU, and generating third program flow trace data whenever a stack for storing instruction addresses of the program is manipulated, the manipulation occurring after a CALL instruction to a function or subroutine of the program is executed by the CPU and before a RET instruction is executed by the CPU. The subset of indirect branch instructions excludes RET indirect branch instructions of any function or subroutine for which the stack is not manipulated after a CALL instruction to the functions or subroutines is executed by the CPU and before the RET instruction is executed by the CPU. | 06-09-2011 |
